A Generator for Time-Predictable Code

Prokesch, Daniel; Hepp, Stefan; Puschner, Peter

doi:10.1109/isorc.2015.40

Cited by 15 publications

(12 citation statements)

References 17 publications

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“…For our experiment we used the Mälardalen WCET benchmarks [21]. We generated the code for the benchmarks with the single-path code generator of the Patmos compiler for the T-CREST platform, which is based on LLVM 3.4 [6]. Following the code generation, we analyzed the binary outputs and generated the RPT for each benchmark.…”

Section: Discussionmentioning

confidence: 99%

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Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Cilku

Puffitsch

Prokesch

et al. 2017

2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)

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Deriving the Worst-Case Execution Time (WCET) of a task is a challenging process, especially for processor architectures that use caches, out-of-order pipelines, and speculative execution. Despite existing contributions to WCET analysis for these complex architectures, there are open problems. The singlepath code generation overcomes these problems by generating time-predictable code that has a single execution trace. However, the simplicity of this approach comes at the cost of longer execution times. This paper addresses performance improvements for singlepath code. We propose a time-predictable memory hierarchy with a prefetcher that exploits the predictability of execution traces in single-path code to speed up code execution. The new memory hierarchy reduces both the cache-miss penalty time and the cachemiss rate on the instruction cache. The benefit of the approach is demonstrated through benchmarks that are executed on an FPGA implementation.

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Section: Discussionmentioning

confidence: 99%

“…The generator for single-path conversion has already been implemented in a compiler back-end [6]. Without going into too much detail, we present the main rules of the single-path conversion in the following.…”

Section: A Single-path Paradigmmentioning

confidence: 99%

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Cilku

Puffitsch

Prokesch

et al. 2017

2017 IEEE 20th International Symposium on Real-Time Distributed Computing (ISORC)

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“…The Patmos compiler can generate single-path code in an automated way [44]. It implements the single-path code transformation in the backend and operates on the control flow graph representation rather than on the source code.…”

Section: Single-path Code Generationmentioning

confidence: 99%

“…Only a simple instruction scheduler for the dualissue feature of Patmos has been developed. Within this project most of the compiler work has been focused on integration with worst-case execution time analysis [48,26], single-path code generation [44], and function splitting [24]. Future work on the compiler is necessary for using the second pipeline more efficiently, e.g., by software pipelining [34] and trace [18] or superblock [28] scheduling.…”

Section: Average-case Performancementioning

confidence: 99%

Patmos: a time-predictable microprocessor

et al. 2018

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“…Predicates are used by the Patmos compiler when generating single-path code [3]. However, the dual-issue pipeline of Patmos is not explored when generating single-path code.…”

Section: Introductionmentioning

confidence: 99%

Towards Dual-Issue Single-Path Code

Maroun

Schoeberl

Puschner

2020

2020 IEEE 23rd International Symposium on Real-Time Distributed Computing (ISORC)

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The Patmos instruction-set architecture is designed for real-time systems. As such, it has features that increase the predictability of code running on it. One important feature is its dual-issue pipeline: instructions may be organized in bundles of two that are issued and executed in parallel. This increases the throughput of the processor in a predictable manner, but only if the compiler makes use of it.Single-path code is a code-generation technique that produces predictable executions by always following the same trace of instructions. The Patmos compiler can already produce singlepath code, but it does not use the second issue slot available in the processor. This is less than ideal because the singlepath transformation results in code that has a high degree of instruction-level parallelism.In this paper, we present a single-path code generator that can produce bundled instructions. It includes generic support for bundling algorithms, such that implementing them is simple and does not require changing other parts of the compiler.We also present one such bundling algorithm plugged into the single-path code generator. With it, we show that we can produce dual-issue instructions to improve performance. Index Terms-real-time systems, time-predictable computer architecture, single-path code generation.

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A Generator for Time-Predictable Code

Cited by 15 publications

References 17 publications

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Improving Performance of Single-Path Code through a Time-Predictable Memory Hierarchy

Patmos: a time-predictable microprocessor

Towards Dual-Issue Single-Path Code

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