A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

Urard, Pascal; Paumier, L.; Viollet, Malika; Lantreibecq, E.; Michel, H; Muroor, Srikanth; Coates, Benjamin; Gupta, B.

doi:10.1109/isscc.2004.1332775

Cited by 15 publications

(4 citation statements)

References 3 publications

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“…If the total number of data block used in the simulation is increased, the error floor would be reached [15] which is obvious in Fig. 13 when K=512 under AWGN channel.…”

Section: Performance Of Different Max* Operatorsmentioning

confidence: 98%

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

ZHANG¹,

HU²,

Chen³

2014

JESTR

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With the evolution of wireless communication systems, it is increasingly difficult for Application Specific Integrated Circuit (ASIC) solutions to meet the daily changing requirements. A network on chip (NOC) multi-core processor based on message-passing programming model is designed to implement the LTE-A turbo decoder in a parallel mode using pure Software Defined Radio (SDR) approach. The NOC is well balanced between the hardware and software design with a high degree of programmability and re-configurability. According to the features of the NOC multi-core processor, the implementation of turbo decoder is optimized to reduce the computational complexity and to increase the parallelization. Several aspects of turbo decoder are investigated in software radio approach rather than hardware. Compared with the results of the software simulation and the Field Programmable Gate Array (FPGA) demonstration, the NOC multicore processor is flexible to realize the proposed turbo decoding algorithm. In addition, our solution has comparable performance with other published ones.

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“…If the total number of data block used in the simulation is increased, the error floor would be reached [15] which is obvious in Fig. 13 when K=512 under AWGN channel.…”

Section: Performance Of Different Max* Operatorsmentioning

confidence: 98%

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

ZHANG¹,

HU²,

Chen³

2014

JESTR

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“…The measurement result indicates that the power consumption of Design-I is 275 mW with 1.32 V supply at 160 Mb/s, and the energy efficiency is 0.22 nJ/b/iter. Table V lists the comparison of the proposed decoders with three published works [33]- [35]. In the parallel architecture, the speedup in throughput will be larger than the growth in power, implying that our designs achieve the best energy efficiency among available solutions.…”

Section: B Influence In the Small Sub-blockmentioning

confidence: 99%

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

Wong

Lai

Lin

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.

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“…The design was realized using a Matlab-to-RTL [6] flow for direct mapping of the datapath description into RTL. In order to respond quickly to further standard revisions, the RTL of this implementation is generic and parameterized.…”

Section: Design Flowmentioning

confidence: 99%

A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

Urard

Paumier

Georgelin

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both Low-Density Parity Check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz. Categories and Subject Descriptors [Design]:Best of wireless at ISSCC'05. An example of highcomplexity algorithm implemented in two different silicon technologies using an original Matlab-2-RTL methodology.

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A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder

Cited by 15 publications

References 3 publications

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3)

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