A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors

Sahu, Aryabartta; BALAKRISHNAN, BALAKRISHNAN; Panda,

doi:10.1109/date.2009.5090813

Cited by 5 publications

(3 citation statements)

References 14 publications

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“…Such applications include bio-informatics, weather forecasting, image processing, cryptography, web applications etc. Many hardware platforms and clusters have been developed with a variety of features and capabilities [1][2] [3]. These platforms contain many-core as well as heterogeneous architectures.…”

Section: Introductionmentioning

confidence: 99%

Performance Enhancemnt of Map-Reduce Framework on GPU

Parakh

Balakrishnan²,

Paul³

2013

Artificial Intelligence and Applications / 794: Modelling, Identification and Control / 795: Parallel and Distributed Computing

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The objective of this work is to get benefit of advancement in GPU technologies in the state of art software framework. We have analyzed the existing map-reduce (MR) framework and modify the same for new GPU architectures. We have identified some significant possibilities for improvement. These improvements are mainly in the context of the different GPU architectures, which were introduced after the development of the MR framework. Our experiments show an average of 2.5x speedup of MR framework on these architectures. Cache reconfiguration is also investigated in this work. We have achieved performance benefit ranging from 10% to 200% for various cache sizes. Based on the above analysis, three techniques have been developed for the performance enhancement of MR framework. First, we exploited the concept of principle of locality by code restructure. We have saved over 32% cache miss per thread. Second, we have reduced the number of comparisons per thread in group phase. Our optimized group phase gives an average of 1.5x speed up. In third optimization, we have performed delayed writing during mapperCount function and make this function as cache sensitive. This reduces significant cache misses and improves the execution time by 10% to 25% for this function.

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Section: Introductionmentioning

confidence: 99%

Performance Enhancemnt of Map-Reduce Framework on GPU

Parakh

Balakrishnan²,

Paul³

2013

Artificial Intelligence and Applications / 794: Modelling, Identification and Control / 795: Parallel and Distributed Computing

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“…Also in this case, these techniques adopt a two-stage approach to perform first the estimation of the single tasks and then of the entire application. For example, [12] exploits the intermediate representation of the SUIF compiler [24] to estimate the execution time of each task and, then, interval analysis to predict the execution time of the whole application. In a similar way, in [25], GCC is modified to automatically generate the workload models of the tasks, while [26] combines performance estimation of single processors to estimate the performance of JPEG encoder and decoder applications on a pipelined MPSoC.…”

Section: Related Workmentioning

confidence: 99%

“…Multiple techniques have been proposed for estimating the performance of a task graph and most of them model the task execution time as a constant value [12] or as a stochastic variable [9]. These task estimations are then combined to estimate the execution time of the entire application, but without considering code correlations that may exist [13].…”

Section: Introductionmentioning

confidence: 99%

Performance Estimation of Task Graphs Based on Path Profiling

Lattuada

Pilato

Ferrandi

2015

Int J Parallel Prog

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Correctly estimating the speed-up of a parallel embedded application is crucial to efficiently compare different parallelization techniques, task graph transformations or mapping and scheduling solutions. Unfortunately, especially in case of control-dominated applications, task correlations may heavily affect the execution time of the solutions and usually this is not properly taken into account during performance analysis. We propose a methodology that combines a single profiling of the initial sequential specification with different decisions in terms of partitioning, mapping, and scheduling in order to better estimate the actual speed-up of these solutions. We validated our approach on a multi-processor simulation platform: experimental results show that our methodology, effectively identifying the correlations among tasks, significantly outperforms existing approaches for speed-up estimation. Indeed, we obtained an absolute error less then 5% in average, even when compiling the code with different optimization levels.

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