A GPU Implementation of a MAP Decoder for Synchronization Error Correcting Codes

Briffa, Johann A.

doi:10.1109/lcomm.2013.031913.130203

Cited by 8 publications

(24 citation statements)

References 15 publications

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“…The throughput results are shown in Figure 10. We can observe that the throughput performance (i) increases with the increase in the number of concurrently executable sub-codewords, (ii) decreases more and more slowly by increasing the number of iterations, (iii) is very similar when P is equal to 8,16, and 32, which means that the performance does not improve consistently by increasing P due to the limited share memory of GPU. We provide the source code of our parallel turbo algorithm so that researchers can master it in a short time.…”

Section: Decoder Throughputmentioning

confidence: 97%

“…Many studies focus on the receiver end, particularly on the turbo decoder . Lee et al designed the space exploration of the turbo decoding algorithm on GPUs.…”

Section: Introductionmentioning

confidence: 99%

“…Cho and Sun presented high‐throughput GPU based turbo decoding software to aid the development of very low error rate block turbo codes. Briffa proposed an optimized parallel implementation of a flexible turbo decoder using MAP algorithm for synchronization error correcting codes, supporting a very wide range of code sizes and channel conditions. These works significantly improve the process of accelerating the turbo decoder.…”

Section: Introductionmentioning

confidence: 99%

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An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Wang

et al. 2018

Concurrency and Computation

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The second-generation digital video broadcasting return channel via satellite (DVB-RCS2) is a promising real-time wireless protocol that has been widely used in many applications, such as video conferences, video feeds, and video multicasting. However, the receiver end of DVB-RCS2 is time consuming and should be accelerated by high-performance processing systems. Today, graphic processing units (GPUs) have been applied in communication systems due to high parallel capability and processing throughput. In this study, we design a novel pipeline of the receiver on the CPU-GPU platform. Moreover, we propose a CPU-GPU hybrid strategy to fully utilize resources and reduce communication latency. Compared with the parallel turbo decoder proposed in other work on the same platform, our parallel implementation achieves higher throughput. For the entire DVB-RCS2 receiver, compared with the non-pipelined serial and non-pipelined parallel algorithms, our proposed pipeline obtains 20 times and 6 times speedup, respectively.In addition, the latency of our implementation is lower than that of non-pipelined CPU-GPU implementation, which is equal to 1.06 ms. KEYWORDSCPU-GPU hybrid platform, pipeline, real-time receiver, software defined radio INTRODUCTIONOver the past decade, digital video broadcasting return channel via satellite (DVB-RCS) and its second generation, DVB-RCS2, have gained rapid prominence and support from governments and industries due to low-cost, high-performance, and reliable internet protocol (IP) networks through very small aperture terminals (VSATs). DVB-RCS2 specifies new technology that provides significant advances in time division multiple address (TDMA) performance for improved efficiency, increased throughput, and greater network reliability than DVB-RCS. DVB-RCS2 provides solutions for high-speed Internet access, video services, voice over IP, and global system for mobile communication backhaul used by the maritime industry, energy sector, utility companies, and global corporations. To the best of our knowledge, all services supported by DVB-RCS2 need low latency and high throughput and must provide real-time capability. Although the receive throughput of DVB-RCS2 is important, it cannot achieve high performance on a CPU platform. The graphic processing unit (GPU) provides a new platform to accelerate the wireless applications in software-defined radio. Compared to a CPU, GPU is a highly parallel, multi-threaded, multi-core processor with tremendous computational power and very large memory bandwidth. Thus, GPU is suitable in performing computation-intensive and highly parallel tasks.For convenience, we use the demodulator to represent all modules of the receiver except for the turbo decoder, as shown in Figure 2. By analyzing the running time of each part on the receiver, we find that the decoder is the most time-consuming part, so it has to be accelerated on the CPU-GPU platform. In fact, numerous studies have focused on how to accelerate the turbo decoder using the CPU-GPU platform. [1][2][3][4][5]...

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Section: Decoder Throughputmentioning

confidence: 97%

“…Many studies focus on the receiver end, particularly on the turbo decoder . Lee et al designed the space exploration of the turbo decoding algorithm on GPUs.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Wang

et al. 2018

Concurrency and Computation

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“…We have in previous papers extended the work of Davey-MacKay, proposing a maximum a posteriori (MAP) decoder [13], improved code designs [14], [15], as well as a parallel implementation of the MAP decoder resulting in speedups of up to two orders of magnitude [16]. However, these papers were restricted to the case where the frame boundaries were known by the decoder.…”

Section: Introductionmentioning

confidence: 99%

Time‐varying block codes for synchronisation errors: maximum a posteriori decoder and practical issues

Briffa

Buttigieg

Wesemeyer

2014

J. eng.

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In this paper we consider Time-Varying Block (TVB) codes, which generalize a number of previous synchronization error-correcting codes. We also consider various practical issues related to MAP decoding of these codes. Specifically, we give an expression for the expected distribution of drift between transmitter and receiver due to synchronization errors. We determine an appropriate choice for state space limits based on the drift probability distribution. In turn, we obtain an expression for the decoder complexity under given channel conditions in terms of the state space limits used. For a given state space, we also give a number of optimizations that reduce the algorithm complexity with no further loss of decoder performance. We also show how the MAP decoder can be used in the absence of known frame boundaries, and demonstrate that an appropriate choice of decoder parameters allows the decoder to approach the performance when frame boundaries are known, at the expense of some increase in complexity. Finally, we express some existing constructions as TVB codes, comparing performance with published results, and showing that improved performance is possible by taking advantage of the flexibility of TVB codes.

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“…It runs on both Windows and Linux and can also use NVIDIA GPUs using CUDA [8]. It has been developed over more than 15 years by the first author and was used successfully in a number of papers [9–13]. The source code has been released under the GNU General Public Licence version 3 (or later) and can be found, together with its documentation, at: https://github.com/jbresearch/simcommsys.…”

Section: Introductionmentioning

confidence: 99%

SimCommSys: taking the errors out of error‐correcting code simulations

Briffa

Wesemeyer

2014

J. eng.

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In this paper we present SimCommSys, a Simulator of Communication Systems that we are releasing under an open source license. The core of the project is a set of C++ libraries defining communication system components and a distributed Monte Carlo simulator. Of principal interest is the error-control coding component, where various kinds of binary and nonbinary codes are implemented, including turbo, LDPC, repeataccumulate, and Reed-Solomon. The project also contains a number of ready-to-build binaries implementing various stages of the communication system (such as the encoder and decoder), a complete simulator, and a system benchmark. Finally, Sim-CommSys also provides a number of shell and python scripts to encapsulate routine use cases. As long as the required components are already available in SimCommSys, the user may simulate complete communication systems of their own design without any additional programming. The strict separation of development (needed only to implement new components) and use (to simulate specific constructions) encourages reproducibility of experimental work and reduces the likelihood of error. Following an overview of the framework, we provide some examples of how to use the framework, including the implementation of a simple codec, the specification of communication systems and their simulation.

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A GPU Implementation of a MAP Decoder for Synchronization Error Correcting Codes

Cited by 8 publications

References 15 publications

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

An efficient CPU‐GPU hybrid parallel implementation for DVB‐RCS2 receiver

Time‐varying block codes for synchronisation errors: maximum a posteriori decoder and practical issues

SimCommSys: taking the errors out of error‐correcting code simulations

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