A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks

Abstract

Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Network-on-Chip (NoC) architectures are required to not only provide ultra-low latency, but also occupy a small footprint and consume as little energy as possible. Further, reliability is rapidly becoming a major challenge in deep sub-micron technologies due to the increased prominence of permanent faults resulting from accelerated aging effects and manufacturing/testing challenges.Towards the goal of designing low-latency, energyefficient and reliable on-chip communication networks, we propose a novel fine-grained modular router architecture. The proposed architecture employs decoupled parallel arbiters and uses smaller crossbars for row and column connections to reduce output port contention probabilities as compared to existing designs. Furthermore, the router employs a new switch allocation technique known as "Mirroring Effect" to reduce arbitration depth and increase concurrency. In addition, the modular design permits graceful degradation of the network in the event of permanent faults and also helps to reduce the dynamic power consumption. Our simulation results indicate that in an 8 × 8 mesh network, the proposed architecture reduces packet latency by 4-40% and power consumption by 6-20% as compared to two existing router architectures. Evaluation using a combined performance, energy and fault-tolerance metric indicates that the proposed architecture provides 35-50% overall improvement compared to the two earlier routers. *

NoCGuard: A Reliable Network-on-Chip Router Architecture

“…We exploit the double routing strategy of [23] with the RC borrowing strategy. The generic router uses a lookahead routing mechanism.…”

“…On the other hand, if an Idle RC was found instantly, the same one extra cycle was consumed. Thus, the use of both strategies gives high reliability as compared to the use of only double routing strategy as in RoCo [23] and HPR [29] router. To detect faults in the RC unit, we use NoCAlert [34] invariance checkers.…”

“…Thus, on average 28.5 faults cause the failure of the NoCGuard router. We compare MDTF of our NoCGuard router with the existing reliable routers such as BulletProof [22], RoCo [23], Vicis [24], PVS [26], REPAIR [25], SHIELD [28], DRS [27] and HPR [29]. From Figure 10, it is evident that the MDTF of NoCGuard is greater than the existing reliable router architectures.…”

Critical-Path Driven Routers for on-Chip Networks

“…The router has dynamic arbitration which is deterministic and fair. Kim et al 15 propose a¯ne-grained modular router architecture. The architecture employs decoupled parallel arbiters and uses smaller crossbars for row and column connections to reduce the output port contention.…”

Distributed On-Chip Operating System for Network on Chip

“…Various aspects of NoC designs have been investigated, including performance [1][2][3][4]16,18], power consumption [5][6][7]15,16,18], area-efficient operation [7][8][9] and reliability [10,11,12]. Some commercial products have already made use of such networks [13,14].…”