A graph based processor model for retargetable code generation

Praet, J. Van; Lanneer, D.; Goossens, Gert; Geurts, Werner; Man, H. De

doi:10.1109/edtc.1996.494133

Cited by 20 publications

(13 citation statements)

References 6 publications

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“…Users can define their own constraints in terms of inputs, outputs, and rules (4). Each output and state address expression is assigned or explicitly not assigned (nop rules are implicitly created for this) (5,6). Causal constraints are defined to reflect causal relationships between inputs, outputs, and atomic actions that reflect the flow of data and relationships to rules (8)(9)(10)(11)(12)(13)(14)(15).…”

Section: Figure 5 Example Data Pathmentioning

confidence: 99%

Using minimal minterms to represent programmability

Keutzer

Weber

2005

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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We address the problem of formally representing the programmability of a system. We define the programmability of a system as the set of valid execution paths that can be configured statically by software. We formally represent this programmability as a Boolean function. From this representation, we extract a subset of on-set minterms that we call minimal minterms. We prove that these minimal minterms represent the set of smallest schedulable atomic actions of the system, and that we can use a special generator relation to determine if subsets of these actions can be executed in parallel. We also prove that given an arbitrary Boolean function we can extract the minimal minterms and recreate the entire on-set by applying the generator relation to every element of the power set of the set of minimal minterms. Thus, the minimal minterms represent the complete instruction set supported by the system, and the generator relation represents the inherent parallelism among the instructions. Furthermore, we automatically generate the required software development tools and hardware implementation from this representation of programmability. Finally, we show that we can efficiently compute the minimal minterms and apply the generator relation to verify parallel executions on interesting data path systems.

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Section: Figure 5 Example Data Pathmentioning

confidence: 99%

Using minimal minterms to represent programmability

Keutzer

Weber

2005

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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“…5] uses a specific language called nML for describing target processor architectures. It generates code for a specific ASSP architectural style and therefore employs special code-generation and optimization techniques [90]. The nML language has also been used in a retargetable compiler project at Cadence [91].…”

Section: G Retargetable Compilationmentioning

confidence: 99%

Software synthesis and code generation for signal processing systems

Bhartacharyya

Leupers

Marwedel

2000

IEEE Trans. Circuits Syst. II

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The role of software is becoming increasingly important in the implementation of digital signal processing (DSP) applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state-of-the-art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high-level block-diagram-based modeling of DSP applications; the translation of block-diagram specifications into efficient C programs using global target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors using architecture-specific and retargetable back-end optimizations. We also point out important directions for further investigation.

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“…On the other hand ASIP design systems usually include CHESS [10] or CoSy [11] as retargetable development environments. These environments are not used only for compiler generation but for generating whole tool chain and simulator for desired platform.…”

Section: Introductionmentioning

confidence: 99%

A Retargetable C Compiler for Embedded Systems

Povazan

Popović

Djukic

et al. 2013

2013 3rd Eastern European Regional Conference on the Engineering of Computer Based Systems

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With the expansion of the market of available embedded platforms the variety of target architectures is rapidly increasing. Therefore the need for retargetable software development tools has never been greater. The C compiler, probably the most significant development tool for embedded systems, is required to be quickly and easily adaptable for new architectures. This paper describes one such generic C compiler which has been adapted for Crystal 32-bit and MIPS 32-bit as two different target platforms. The aim of this paper is to prove that the compiler has modifiable infrastructure and can be easily adapted to support new architectures, as well as to improve the compiler in terms of extending this capability. The compiler has been tested for correctness for both architectures. For Crystal 32-bit platform quality testing has also been performed and all test results showed remarkable results. On the other hand, for MIPS 32-bit architecture, for which full compiler support is still an ongoing process, correctness tests were performed with exceptions of C language aspects which are not commonly used in embedded system applications. The analyses of these tests showed convincing results for embedded domain and promising results for reaching full MIPS 32-bit support.

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A graph based processor model for retargetable code generation

Cited by 20 publications

References 6 publications

Using minimal minterms to represent programmability

Using minimal minterms to represent programmability

Software synthesis and code generation for signal processing systems

A Retargetable C Compiler for Embedded Systems

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