A hardware approach to self-testing of large programmable logic arrays

A minimal universal test set for self-test of EXOR-Sum-of-Products circuits

“…Reddy's technique is good for self testing because as shown by Daehn and Mucha [8], the entire test sequence can be inexpensively generated by a modified LFSR using a NOR gate and a shift register. However, as shown in Table 1, the number of terms in a PPRM is usually higher than the number of FPRM or GRM terms, and much higher than the number of ESOP terms [5].…”

“…Daehn and Mucha designed a simple BIST circuit to test PLAs [8]. They used LFSRs and NOR gates to generate regular test patterns such as a walking-one test sequence.…”

Area reduction techniques for BIST PLA's

“…Many solutions to this problem has been proposed in the past [l, 2, 31; the most effective one has been presented by Daehn and Mucha in [4]; the technique is based on the partitioning of the PLA and on the employment of Built-In Logic Block Observers (BILBO's), and it is still used to generate test pattern inputs and compreslr test responses on-chip. A disadvantage of the BILBO approach is that it is very area consuming, especially when shift registers are used to implement the Built-In Self Testing (BIST) mechanism.…”

“…A modification of the BILBO technique, called Modified Self-Testing PLA, has been presented by the authors in [5]. Such a technique, which makes use of the 1/0 registers of the PLA to realize the on-chip testing circuitry, is more effective than the one presented in [4], because the area of the overall circuit turns out to be not too penalized by the introduction of the testing logic. In this paper we describe some variants to the method presented in [5] which allow a further reduction of the chip area needed to realize the BIST circuitry.…”