A hardware implementation of MD4-family hash algorithms

Dominikus, Sandra

doi:10.1109/icecs.2002.1046454

Cited by 65 publications

(43 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The performance of the separate implementation SHA-2(256) is slightly higher compared with the performance of the proposed system [24]. Comparing with previous implementations published in [6] the proposed system is 277 and 417% faster. The work of [14] achieves higher throughput compared with the proposed systems at about 3% and 36%, but with lower operation frequency at about 49% times.…”

Section: Introductionmentioning

confidence: 39%

“…The proposed system throughput is worst In addition, comparisons of the proposed system implementation with other previous works are illustrated in the Table 4. Since the SHA-2 hash family is a new standard only few related works [6,14] have been published until now in the technical literature. In Table 4 comparisons with hash function standard (SHA-1) implementations [5,6,18,23] are also given.…”

Section: Vlsi Implementation Synthesis Resultsmentioning

confidence: 99%

“…It provides higher supported security level and better hardware performance. In addition, the proposed system performance is much better than the previous SHA-1 standard works, in both software assembly developments [5,18] and hardware implementations [6,23].…”

Section: Introductionmentioning

confidence: 83%

See 2 more Smart Citations

Implementation of the SHA-2 Hash Family Standard Using FPGAs

Sklavos

Koufopavlou

2005

J Supercomput

View full text Add to dashboard Cite

The continued growth of both wired and wireless communications has triggered the revolution for the generation of new cryptographic algorithms. SHA-2 hash family is a new standard in the widely used hash functions category. An architecture and the VLSI implementation of this standard are proposed in this work. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256, 384 and 512) of the SHA-2 standard. The proposed system is compared with the implementation of each hash function in a separate FPGA device. Comparing with previous designs, the introduced system can work in higher operation frequency and needs less silicon area resources. The achieved performance in the term of throughput of the proposed system/architecture is much higher (in a range from 277 to 417%) than the other hardware implementations. The introduced architecture also performs much better than the implementations of the existing standard SHA-1, and also offers a higher security level strength. The proposed system could be used for the implementation of integrity units, and in many other sensitive cryptographic applications, such as, digital signatures, message authentication codes and random number generators.

show abstract

Section: Introductionmentioning

confidence: 39%

Section: Vlsi Implementation Synthesis Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Implementation of the SHA-2 Hash Family Standard Using FPGAs

Sklavos

Koufopavlou

2005

J Supercomput

View full text Add to dashboard Cite

show abstract

“…DES proved to be fastest for ASIC implementations but is insecure. (Savas et al, 2005) 0.9 Gbps (Dominikus, 2002). MD5 2.09 Gbps (Savas et al, 2005) 5.86 Gbps (Joye and Quisquater, 2001) Different platforms have varying requirements.…”

Section: Performance and Security Analysis Of Hardware Implementationsmentioning

confidence: 99%

Overview of securing multimedia content using efficient encryption methods and modes

Singh¹

2017

Int. j. adv. appl. sci.

View full text Add to dashboard Cite

Multimedia comprises of audio, text, image and video. Use of multimedia is increasing because of improvements in hardware, algorithms and networking. Confidentiality of data is the primary concern due to applications in commerce, telemedicine, Internet television, video telephony, multiparty P2P conferences, video on demand and military. Multimedia files are data intensive thus, they need more computational power and consume more memory as compared to ordinary text data. Comparative analysis of vulnerabilities and counter measures are made. In this paper, possibilities of securing multimedia data using various encryption methods and modes are analyzed and compared on the basis of their execution speed, hardware implementation and various attacks. It is found that public key cryptosystems are comparatively slow and they get more vulnerability. Comparative analysis shows that confusion and diffusion are used in many faster cryptosystems to measure the security level. Moreover, hardware implementation (ASIC and FPGA) provides better security than software implementations. ASIC and FPGA implementations had high variation in throughput irrespective of the cryptosystem.

show abstract

“…It calculates a 128-bit digest for an arbitrary l-bit message. It is an enhanced version of its predecessor MD4 [5] [6].The algorithm could be described in two stages: Preprocessing and Hash Computation. Preprocessing involves padding a message, parsing the padded message into m-bit blocks, and setting initialization values to be used in hash computation.…”

Section: Md-5 and Sha-1 Algorithmmentioning

confidence: 99%

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

Thulasimani¹,

Madheswaran²

2010

IJCEE

View full text Add to dashboard Cite

Abstract-Software Radio terminals being able to reconfigure to various radio access systems, will require robust security mechanism to protect the mobile terminals from unauthorized access and to ensure the integrity of internal process involved in reconfiguration when exchanging information with the network. This paper aims to propose an energy efficient reconfigurable hardware architecture which supports data integrity for the secured downloading of software in reconfigurable receivers.

show abstract

A hardware implementation of MD4-family hash algorithms

Cited by 65 publications

References 4 publications

Implementation of the SHA-2 Hash Family Standard Using FPGAs

Implementation of the SHA-2 Hash Family Standard Using FPGAs

Overview of securing multimedia content using efficient encryption methods and modes

A Low-Power and High Throughput Reconfigurable Data Integrity Unit for Software Radio

Contact Info

Product

Resources

About