A hardware implementation of the MCAS synchronization primitive

Patel, Srishty; Kalayappan, Rajshekar; Mahajan, Ishani; Sarangi, Smruti R.

doi:10.23919/date.2017.7927120

Cited by 8 publications

(9 citation statements)

References 8 publications

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“…Patel et al [21] describe a hardware implementation of MCAS, a multi-word CAS operation for multi-core systems. They find that on average, their implementation is up to 13.8 times faster than locks with critical sections spanning from 40 to 345 cycles.…”

Section: Related Workmentioning

confidence: 99%

Hardlock: Real-time multicore locking

Strøm

Sparsø

Schoeberl

2019

Journal of Systems Architecture

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Multiple threads executing on a multicore processor often communicate via shared objects, allocated in main memory, and protected by locks. A lock itself is often implemented with the compare-and-swap operation. However, this operation is retried when the operation fails and the number of retries is unbounded. For hard real-time systems we need to be able to provide worstcase execution time bounds for all operations.The paper presents a time-predictable solution for locking on a multicore processor. Hardlock is an on-chip locking unit that supports concurrent locking without the need to get off-chip. Acquisition of a lock takes 2 clock cycles and release of a lock 1 clock cycle.

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Section: Related Workmentioning

confidence: 99%

Hardlock: Real-time multicore locking

Strøm

Sparsø

Schoeberl

2019

Journal of Systems Architecture

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“…Patel et al [15] propose a special HW instruction to change multiple memory positions atomically, optimizing the synchronization process. This instruction is an extension of the currently widely available compare-and-swap instruction, which is similar to the hardware transactional memory approach [7] where the developer delimits atomic blocks of codes.…”

Section: Related Workmentioning

confidence: 99%

“…Table 4 summarizes the synthesis results showing that our solution increases by 36% the basic NI area including the local SPM. However, the overhead can be negligible compared to the chip area; for a 400 mm 2 chip [15], 64 Enhanced NI have an overhead of 0.03%.…”

Section: Subutai-hwmentioning

confidence: 99%

“…Although it is feasible to relax the specification of such structures, the consequence is a significant source code redesign. The majority of recent works requires source code meddling, which is notoriously a hard task [13] [15]. We developed Subutai, a hardware-software solution that tackles the synchronization overhead by offloading its processing to a new low-latency NI enhanced with dedicated resources.…”

Section: Introductionmentioning

confidence: 99%

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Subutai

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et al. 2018

Proceedings of the 55th Annual Design Automation Conference

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Parallel applications are essential for efficiently using the computational power of a Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. Moreover, synchronization is also a bottleneck due to sequential access to shared memory. We address this issue and introduce "Subutai", a hardware/software (HW/SW) architecture designed to distribute essential synchronization mechanisms over the Network-on-Chip (NoC). It includes Network Interfaces (NIs), drivers and a custom library of a NoC-based MP-SoC architecture that speeds up the essential synchronization primitives of any legacy parallel application. Besides, we provide a fast simulation tool for parallel applications and a HW architecture of the NI. Experimental results with PARSEC benchmark show an average application speedup of 2.05 compared to the same architecture running legacy SW solutions for 36% overhead of HW architecture.

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“…Patel et al [3] describe a hardware implementation of a multi-word CAS (MCAS) for multi-core systems. They find that on average their implementation is up to 13.8 times faster than locks.…”

Section: Related Workmentioning

confidence: 99%

Hardlock: A Concurrent Real-Time Multicore Locking Unit

Strøm

Schoeberl

2018

2018 IEEE 21st International Symposium on Real-Time Distributed Computing (ISORC)

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To use multicore processors, an application needs to split computation into several threads that execute on different processing cores. As those threads work together towards a common goal, they need to exchange data in a controlled way. A common communication paradigm between cooperating threads is using shared data structures protected by locks. Implementing a lock on top of shared memory can easily result in a bottleneck on a multicore processor due to the congestion on the shared memory. However, the number of locks in use is usually low and using the large external memory to support locks is over-provisioning a resource. This paper presents an efficient implementation of locking by providing dedicated hardware support for locking on-chip. This locking unit supports a restricted number of locks without the need to get off-chip. The unit can process lock acquisitions in 2 clock cycles and releases in 1 clock cycle.

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A hardware implementation of the MCAS synchronization primitive

Cited by 8 publications

References 8 publications

Hardlock: Real-time multicore locking

Hardlock: Real-time multicore locking

Subutai

Hardlock: A Concurrent Real-Time Multicore Locking Unit

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