2008
DOI: 10.1007/978-3-540-85857-7_7
|View full text |Cite
|
Sign up to set email alerts
|

A Hardware-Software Design Framework for Distributed Cellular Computing

Abstract: Abstract. In this article, we describe a novel hardware-software design framework for prototyping cellular architectures in hardware. Based on an extensible platform of about 200 FPGAs, configured as a networked structure of processors, the hardware part of this computing framework is backed by an extensible library of software components that provides primitives for efficient inter-processor communication and distributed computation. This dual software-hardware approach allows a very quick exploration of diff… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
3
0

Year Published

2010
2010
2013
2013

Publication Types

Select...
2
1

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(3 citation statements)
references
References 15 publications
0
3
0
Order By: Relevance
“…This could benefit from a global clock, i.e. synchronized cycles of movements as described in [23]. Once a synchronization would be implemented, the overall setup becomes deterministic, at any crucial point in time (beginning of cycles) distances between metamodules are known, communicated, and a consensus could be made.…”
Section: Discussion and Future Workmentioning
confidence: 99%
“…This could benefit from a global clock, i.e. synchronized cycles of movements as described in [23]. Once a synchronization would be implemented, the overall setup becomes deterministic, at any crucial point in time (beginning of cycles) distances between metamodules are known, communicated, and a consensus could be made.…”
Section: Discussion and Future Workmentioning
confidence: 99%
“…The transport triggered architecture (TTA) was created in the 1980's [11] and usually contains an instruction decoder, an interconnection network and a number of functional units (FUs), as shown in figure. 2 [12]. Functional units and the decoder are connected through data buses and address buses, a single data/address bus pair is called a slot, and a processor can have multiple slots to allow parallel processing to occur.…”
Section: Smove Transport Triggered Architecturementioning
confidence: 99%
“…This could require a global clock, i.e. synchronized cycles of movements as described in [36]. Dead-locks at the assembly phase of a structure happen as a result of the (currently hand-coded and) non-optimized seeding order, and the orientation of the foot hemispheres of metamodules within the assembled structure.…”
mentioning
confidence: 99%