A hardware/software platform for QoS bridging over multi-chip NoC-based systems

Nejad, Ashkan Beyranvand; Molnos, Anca; Martinez, Matias Escudero; Goossens, Kees

doi:10.1016/j.parco.2013.04.011

Cited by 7 publications

(1 citation statement)

References 43 publications

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“…It uses a streaming protocol, uniform data widths and a single clock frequency. An optional Ethernet bridge can be added to connect two NoCs residing on separate chips [7].…”

Section: Communication Corementioning

confidence: 99%

The CompSOC design flow for virtual execution platforms

Goossens

Åkesson

Koedam

et al. 2013

Proceedings of the 10th FPGAworld Conference

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Designing a SoC for applications with mixed time-criticality is a complex and time-consuming task. Even when SoCs are built from components with known real-time properties, they still have to be combined and configured correctly to assert that these properties hold for the complete system, which is non trivial. Furthermore, applications need to be mapped to the available hardware resources and correctly integrated with the SoC's software stack, such that the realtime requirements of the applications are guaranteed to be satisfied. However, as systems grow in complexity, the design and verification effort increases, which makes it difficult to satisfy the tight time-to-market constraint.Design tools are essential to speed up the development process and increase profit. This paper presents the design flow for the CompSOC FPGA platform: a template for SoCs with mixed time-criticality applications. This work outlines how the development time of such a platform instance is reduced by means of its comprehensive tool flow, that aids a system designer in creating hardware, the associated software stack, and application mapping.

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“…It uses a streaming protocol, uniform data widths and a single clock frequency. An optional Ethernet bridge can be added to connect two NoCs residing on separate chips [7].…”

Section: Communication Corementioning

confidence: 99%