A Heterogeneous Parallel Processor for High-Speed Vision Chip

Yang, Jie; Yang, Yongxing; Chen, Zhe; Liu, Liyuan; Liu, Jian; Wu, Nanjian

doi:10.1109/tcsvt.2016.2618753

Cited by 20 publications

(27 citation statements)

References 38 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Besides, our theory is also suitable for the modified IF neuron with "reset by subtraction" [31], which does not have the lowest limitation V min of membrane potential and their residual parts after firing and reset still remain in membrane potential. The total residual of modified IF neuron only contains the third term in (6). Therefore, the approximation relation derived from our theory can cover the previous theory proposed by [31] and is more general.…”

Section: Conversion Theorysupporting

confidence: 56%

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks

Yang

Zhang

Zhu

et al. 2020

Sci. China Inf. Sci.

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Conversion Theorysupporting

confidence: 56%

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks

Yang

Zhang

Zhu

et al. 2020

Sci. China Inf. Sci.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The hierarchical parallel processing layers can store the image data and implements image processing algorithms in parallel. Many FD vision chips have been reported [4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19]. The early vision chips consist of a two-dimensional (2D) array of processing elements (PEs) [6][7][8][9][10][11].…”

Section: Neuromorphic Vision Chipsmentioning

confidence: 99%

“…It can track a high-speed moving target under complex conditions. To improve the processing accuracy and efficiency, a heterogeneous parallel processor for high speed vision chip was proposed [19]. It uses patch processing unit (PPU) array processor to replace the RP array processor in [17].…”

Section: Fd Vision Chipsmentioning

confidence: 99%

See 1 more Smart Citation

Neuromorphic vision chips

2018

Sci. China Inf. Sci.

Self Cite

View full text Add to dashboard Cite

The paper reviews the progress of neuromorphic vision chip research in decades. It focuses on two kinds of the neuromorphic vision chips: frame-driven (FD) and event-driven (ED) vision chips. The FD and ED vision chips are very different from each other in system architecture, image sensing, image information coding, image processing algorithm, design methodology. The vision chips can overcome serial data transmission and processing bottlenecks in traditional image processing systems. They can perform the high speed image capture and real-time image processing operations. This paper selects two typical chips from the two kinds of vision chips, respectively, and introduces their architectures, image sensing schemes, image processing processors and system operation. The FD neuromorphic reconfigurable vision chip comprises a high speed image sensor, a processing element array and self-organizing map neural network. The FD vision chip has the advantages in image resolution, static object detection, time-multiplex image processing, and chip area. The ED neuromorphic vision chip system is based on address-event-representation image sensor and event-driven multi-kernel convolution network. The ED vision chip has the advantages in fast sensing, low communication bandwidth, brain-like processing, and high energy efficiency. Finally, this paper discusses the architecture and the challenges of the future neuromorphic vision chip and indicates that the reconfigurable vision chip with left-and right-brain functions integrated in the three dimensional (3D) large-scale integrated circuit (LSI) technology becomes a trend of the research on the vision chip.

show abstract

“…A hierarchical parallel vision processor is a device that integrates multiple levels of processors exhibiting different parallelisms and complexities. Such processors can be extensively applied in areas, including industrial automation and security monitoring [1,2,3,4,5,6]. With the rapid growth of computation requirements in space imageprocessing missions [7,8,9], vision processors exhibit excellent prospects for performing various image-processing tasks.…”

Section: Introductionmentioning

confidence: 99%

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

Zhang

et al. 2019

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

This paper proposes novel single event upset (SEU) failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. To automatically evaluate the SEU failure probability and identify all the critical elements in a processor, complementary fault injection methods based on logic circuit simulator and Perl script are proposed. These methods can be used to randomly inject faults into D flip-flops (DFFs) and various types of memory at the register transfer level (RTL) as well as to evaluate the vision processor performance. Based on the evaluation results, an accurate periodic scrubbing technique is proposed to increase the processor availability. The results denote that the peak availability of the processor over a period of one year can be improved from 18% to 99.9% after scrubbing the RISC program memory for a period of 10 4 s. Therefore, we can improve the fault-tolerance performance of a vision processor while avoiding unnecessary area and power costs using techniques ranging from evaluation to mitigation.

show abstract

A Heterogeneous Parallel Processor for High-Speed Vision Chip

Cited by 20 publications

References 38 publications

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks

Deterministic conversion rule for CNNs to efficient spiking convolutional neural networks

Neuromorphic vision chips

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors

Contact Info

Product

Resources

About