A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System

Zhang, Haifeng; Wu, Xiaoti; Du, Yuyu; Guo, Hao; Li, Chuxi; Yuan, Ye; Meng, Zhongjie; Zhang, Shengbing

doi:10.3390/s21196491

Cited by 5 publications

(5 citation statements)

References 27 publications

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“…An effective DNN (deep neural network)-application-focused RISC-V processor was proposed by Zhang H. et al [10]. The work demonstrated promising capabilities in effec-tively executing DNN tasks while minimizing power consumption.…”

Section: Related Workmentioning

confidence: 99%

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Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

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Section: Related Workmentioning

confidence: 99%

“…Four quarter rounds in an odd round will operate on those words as defined in (6). QR(0, 4, 8, 12); QR(1, 5, 9, 13); QR (2,6,10,14); QR (3,7,11,15); (6) Additionally, four other quarter rounds in an even round will manipulate those words, as in (7). Two consecutive rounds of this odd round and even round is called a double round.…”

Section: Chachamentioning

confidence: 99%

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Pham

et al. 2023

Future Internet

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“…The authors from [16] proposed a lightweight pipeline integrated deep learning architecture compatible with RISC-V instructions. Their main goal was to improve the computational performance as much as possible under the limit of low power consumption to accelerate the processing of data captured by the sensors.…”

Section: A Risc-v In Sensing Applicationsmentioning

confidence: 99%

Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments

Mattos

Santos

Imianosky

et al. 2023

2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI)

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Sensing systems are present in most application domains, including those in harsh environments. These systems are often designed around processing units sensitive to these environmental conditions. Still, the systems must withstand extreme operational conditions in these environments and maintain consistent measurements. In this work, we present the challenges imposed by radiation effects in sensing applications and discuss the utilization of a fault-tolerant RISC-V System-on-Chip, the HARV-SoC, to mitigate their impact. The HARV-SoC comprises peripherals and the fault-tolerant HARV core, which relies on hardening strategies, such as physical and information redundancy, to meet the requirements of critical applications targeting harsh environments and reduce the propagation of errors. Hence, we guide how to employ the proposed system in sensing applications and empower the community with a new tool for reliability-oriented projects.

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“…With the development of RISC-V, a large number of open-source processor cores have appeared in academic and commercial markets [28]. In recent years, the RISC-V processor has also been deeply studied and applied in the Internet of Things, neural networks, artificial intelligence, and so on [29][30][31][32]. There are not many RISC-V processors with fault-tolerant architecture currently publicly available.…”

Section: Related Workmentioning

confidence: 99%

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Shan-cong

Bao

2021

Electronics

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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

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A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System

Cited by 5 publications

References 27 publications

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

Using HARV-SoC for Reliable Sensing Applications in Radiation Harsh Environments

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

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