A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing

Abstract

A deterministic activity network (DAN) is a collection of activities, each with some duration, along with a set of precedence constraints, which specify that activities begin only when certain others have finished. One critical performance measure for an activity network is its makespan, which is the minimum time required to complete all activities. In a stochastic activity network (SAN), the durations of the activities and the makespan are random variables. The analysis of SANs is quite involved, but can be carried out numerically by Monte Carlo analysis.This paper concerns the optimization of a SAN, i.e., the choice of some design variables that affect the probability distributions of the activity durations. We concentrate on the problem of minimizing a quantile (e.g., 95%) of the makespan, subject to constraints on the variables. This problem has many applications, ranging from project management to digital integrated circuit (IC) sizing (the latter being our motivation). While there are effective methods for optimizing DANs, the SAN op-398 S.-J. Kim et al.timization problem is much more difficult; the few existing methods cannot handle large-scale problems.In this paper we introduce a heuristic method for approximately optimizing a SAN, by forming a related DAN optimization problem which includes extra margins in each of the activity durations to account for the variation. Since the method is based on optimizing a DAN, it readily handles large-scale problems. To assess the quality of the resulting suboptimal designs, we describe two widely applicable lower bounds on achievable performance in optimal SAN design.We demonstrate the method on a simplified statistical digital circuit sizing problem, in which the device widths affect both the mean and variance of the gate delays. Numerical experiments show that the resulting design is often substantially better than one in which the variation in delay is ignored, and is often quite close to the global optimum (as verified by the lower bounds).

Area estimation and optimisation of FPGA routing fabrics

“…GPs are important in practice because some of the same efficient algorithms that are known for solving linear programs can also be applied to GPs, for example the class of interior point methods [8]. In particular, this means that GPs can be solved in polynomial time in theory, and extremely fast in practice [9]. For our purpose, formulation of architecture exploration as a GP would have serious implications for the speed at which the architecture space can be explored: the optimal solution to a GP can be found in time that grows only with √ m and cubically in n + l [8].…”

An Efficient Method for Large-Scale Gate Sizing

“…We call this procedure nonlinear back substitution, because if we consider the problem (7) without the constraints on the minimum gate size, then the solution is given by (8), and is given by the upper triangular matrix equation…”

“…The domain of the function is given by (10) If , the inequality is interpreted as . The function can be viewed as a composition (11) The function is given by (8). The function is a function of , and is implicitly defined as a backward recursion by (9).…”

Determinação de caminhos k-críticos em redes PERT

“…Considerando-se a rede do projeto na forma canônica, dada uma realização t(i, j) T(i, j), para toda atividade (i, j) A, define-se: data mais cedo de um vértice i, denotada por a) E(i) e determinada por E(i) = 0 para i = 1, e , para j = 2, 3,..., n, em que u i são os vértices antecessores imediatos de i, como sendo o primeiro instante no qual todas as atividades que emergem de i podem ser iniciadas, (E(i) é igual à duração do caminho mais longo entre os vértices s e i); primeira destas áreas, pode-se relacionar Kim et al (2007), Ghomi e Rabbani (2001) e Soroush (1994, que citam Dodin (1984). Soroush (1994) apresenta um método para determinar a probabilidade de cumprir prazo de conclusão do projeto cuja construção se assemelha ao processo utilizado por Dodin (1984).…”

“…Ghomi e Rabbani (2001) apresentam um método para identificação da função de distribuição do tempo de conclusão de projetos em redes estocásticas que apresentou, em alguns casos, resultados melhores que aqueles obtidos por Soroush (1994). Kim et al (2007) apresentam uma heurística para a alocação ótima de recursos em projetos para garantir, com alta probabilidade, a sua realização dentro de um prazo pré-definido. Dentre os trabalhos recentes relacionados com a área de eletrônica, pode-se citar Luo et al (2006), referenciando Ju e Saleh (1991), e Borna et al (2005), que referencia Yen et al (1989).…”