A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics

Vaidya, Sumit R.; Dandekar, D. R.

doi:10.1145/1947940.1948020

Cited by 2 publications

(3 citation statements)

References 13 publications

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“…Vedic multiplication is an ancient Indian Mathematics which is based on Urdhva Tiryakbhyam algorithm. The Vedic multiplier is time, area and power efficient due to the gate delay and space increase slowly when increasing the number of Vedic multiplier bit compared to other multipliers [8][9][10]. All the base multipliers consist of AND-gates, compressors, half adders and full adders.…”

Section: Hierarchy Multipliermentioning

confidence: 99%

Speed and area analysis on hierarchy multiplier

Wong

Hussin

2017

EPJ Web Conf.

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Abstract. This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 compressor and multiple compressors. The hierarchy multipliers is optimised in the term of speed or area of hierarchy multiplier by redesigning 4:2 compressor units and introducing a combination of 4:2 compressor and 7:3 compressor units in a Vedic multiplier block. All designs are simulated using Altera Quartus II software. The aim of this paper is to improve the performance in speed by moderately increasing the area without considering the power consumption. The proposed design is 4.5% to 8.3% faster and consumes -0.5% to 5.8% less area.

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Section: Hierarchy Multipliermentioning

confidence: 99%

Speed and area analysis on hierarchy multiplier

Wong

Hussin

2017

EPJ Web Conf.

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“…High speed, less area and low power consumption are ideal case for design. Either two of this parameter become research interest of designer [1,2]. Multiplier takes a significant impact for computational performance.…”

Section: Introductionmentioning

confidence: 99%

“…High speed, less area and low power consumption are ideal case for design. Conventionally, delay time and area size are also reduced to minimize power dissipation [6].…”

Section: Introductionmentioning

confidence: 99%

Power-Effective Vedic-Hierarchical Multiplier

Cheng,

Arshad

2020

IJIE

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The motivation of this project is to design a power effective multiplier without having much drawback in term of time constraint and area utilization. This is due to the overall power dissipation which increases in direct proportion to the increase in power density. The area and time constraint are considered as pertinent design parameters with the increase in market demand for high performance and complex portable systems. The current hierarchical multiplier designs suffer on long critical path and large area utilization. These parameters caused the hierarchical multiplier design to be less effective in term of power saving. The objective of this research is to reduce overall power dissipation and ensure that the multiplierachieve timing requirement. This paper proposes the design 1 by using two 4-bit Binary-to-Excess-One Converter (BEC) instead of an 8-bit BEC. The BEC reduce the critical path and cause low power dissipation. Design 2 which is implementation of Carry Select Adder (CSlA) with tristate buffer is to reduce logic elements. The power dissipation is reduced because of the decrease in the number of logic elements which leads to the lower number of logic gates. Both advantages of design 1 and design 2 are combined to become design 3. Design 3 is the lowest power dissipation design because it consists of the lowest number of logic elements and the shortest critical path. The timing requirement for all designs are met as shown by the positive slack time of 9.034 ns, 8.686 ns and 9.404 ns respectively. The power dissipation of the combinational multipliers designs have been improved to 60.96%, 60.89% and 61.02% respectively.

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A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics

Cited by 2 publications

References 13 publications

Speed and area analysis on hierarchy multiplier

Speed and area analysis on hierarchy multiplier

Power-Effective Vedic-Hierarchical Multiplier

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