A High-Efficiency <i>W</i>-Band Frequency Quadrupler With Current-Reusing Stacked Push–Push Stages

Mensah, Yaw A.; Rao, Sunil G.; Teng, Jeffrey W.; Cressler, John D.

doi:10.1109/lmwt.2022.3226660

Cited by 7 publications

(2 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Section: Introductionmentioning

confidence: 99%

“…Previously, frequency multipliers with high output power have been presented using SiGe and CMOS processes 6–9 . The frequency multipliers are introduced in Mazor et al 6 and Mensah et al 7 which use SiGe process. Their output power can reach 13.5 and 8.7 dBm, which advances the others in CMOS process, 8,9 while its power consumption and dimension are not ideal.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

W‐band ×8 frequency multiplier in 65 nm CMOS with 25% bandwidth and 4.63 dBm output power

Song,

Yu,

Zhao

et al. 2023

Micro & Optical Tech Letters

View full text Add to dashboard Cite

This letter presents an ×8 frequency multiplier for the W‐band wireless satellite communication in the 65 nm complementary metal‐oxide‐semiconductor process. To reduce the power consumption, the proposed frequency multiplier employs only one driven amplifier and three stages of doublers. All doublers adopt balanced structures to increase their robustness. The output buffer is introduced to ameliorate the impedance matching of output port so that the output power of the proposed ×8 frequency multiplier can achieve 4.63 dBm. Through the special design of the interstage impedance matching circuit, the relative 3‐dB bandwidth of the proposed frequency multiplier is over 25% (from 74.8 to 96.2 GHz). The chip also has a small size and low power consumption, which is 1.37 × 0.51 mm2 and 125 mW, respectively.

show abstract

Section: Introductionmentioning

confidence: 99%