A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Johansson, Sofia; Berg, Martin; Persson, Karl‐Magnus; Lind, Erik

doi:10.1109/ted.2012.2231867

Cited by 81 publications

(52 citation statements)

References 14 publications

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“…This result is in line with the work reported in Ref. 21, where evidence of "fast" border traps responding to f > 1 GHz is demonstrated. Unfortunately, the GHz frequency range is not accessible with MFICP.…”

Section: Transient Charging Time and Border Trap Responsesupporting

confidence: 93%

“…A distance (x) for the spatial location of the border traps relative to the In 0.53 Ga 0.47 As interface can be estimated using the relationship 33 x ¼ k lnðt=sÞ; (7) where k is the attenuation coefficient and t is the tunnelling time. Assuming a k value within the typical range of 9.8 Â 10 À9 -1.25 Â 10 À8 cm reported for the Al 2 O 3 / In 0.53 Ga 0.47 As interface [16][17][18]21,30 and considering that N CP saturation is reached at t $ 5 ls (Fig. 6), we obtain a distance x of about 1.6-2.1 Å from the interface.…”

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 71%

“…This range of values is in agreement with other studies of border traps in the high-k/InGaAs system. 18,21,34 It is noted that the discussion of the D bt ÁDt bt ÁDE data relies on the energy vs gate bias and trap density vs energy profiles obtained from a previous C-V study that we performed on the same set of devices as that used in this study. 27 Moreover, since Dt bt cannot be obtained from our ICP-based approach, a value of $ 2 Å is assumed from Ref.…”

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 99%

“…27 Moreover, since Dt bt cannot be obtained from our ICP-based approach, a value of $ 2 Å is assumed from Ref. 21. This assumption is in agreement with the extracted b value of 1.0 (Table I) suggesting a discrete r. Therefore, considering from our previous work 27 that an energy range of $0.8 eV is swept when V g goes from V base ¼ À0.3 V to V peak ¼ 2 V and assuming Dt bt $ 2 Å (Ref.…”

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 99%

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Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Djara

Cherkaoui

Negara

et al. 2015

Journal of Applied Physics

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Original citationDjara, V., Cherkaoui, K., Negara, M. A. and Hurley, P. K. (2015) An alternative multi-frequency inversion-charge pumping (MFICP) technique was developed to directly separate the inversion charge density (N inv ) from the trapped charge density in high-k/ InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). This approach relies on the fitting of the frequency response of border traps, obtained from inversion-charge pumping measurements performed over a wide range of frequencies at room temperature on a single MOSFET, using a modified charge trapping model. The obtained model yielded the capture time constant and density of border traps located at energy levels aligned with the InGaAs conduction band. Moreover, the combination of MFICP and pulsed I d -V g measurements enabled an accurate effective mobility vs N inv extraction and analysis. The data obtained using the MFICP approach are consistent with the most recent reports on high-k/InGaAs. V C 2015 AIP Publishing LLC.

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Section: Transient Charging Time and Border Trap Responsesupporting

confidence: 93%

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 71%

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 99%

Section: Transient Charging Time and Border Trap Responsementioning

confidence: 99%

See 2 more Smart Citations

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Djara

Cherkaoui

Negara

et al. 2015

Journal of Applied Physics

View full text Add to dashboard Cite

show abstract

“…It is noted that CV hysteresis measured at 1 MHz does not capture all border traps, as in practical devices, border traps exist into the oxide, and the density can vary with depth into the oxide, as well as with energy. 32 In a CV sweep, the fast traps, which can respond at frequencies up to the low GHz range, would have emitted the trapped charge just as the reverse sweep is initiated. In addition, a significant quantity of charge is lost during the reverse CV sweep.…”

mentioning

confidence: 99%

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

Peralagu

Millar

et al. 2017

Applied Physics Letters

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This study reports the impact of forming gas annealing (FGA) on the electrical characteristics of sulfur passivated, atomic layer deposited Al2O3 gate dielectrics deposited on (110) oriented n- and p-doped In0.53Ga0.47 As layers metal-oxide-semiconductor capacitors (MOSCAPs). In combination, these approaches enable significant Fermi level movement through the bandgap of both n- and p-doped In0.53Ga0.47 As (110) MOSCAPs. A midgap interface trap density (Dit) value in the range 0.87−1.8×1012 cm−2eV−10.87−1.8×1012 cm−2eV−1 is observed from the samples studied. Close to the conduction band edge, a Dit value of 3.1×1011 cm−2eV−13.1×1011 cm−2eV−1 is obtained. These data indicate the combination of sulfur pre-treatment and FGA is advantageous in passivating trap states in the upper half of the bandgap of (110) oriented In0.53Ga0.47 As. This is further demonstrated by a reduction in border trap density in the n-type In0.53Ga0.47 As (110) MOSCAPs from 1.8×1012 cm−21.8×1012 cm−2 to 5.3×1011 cm−25.3×1011 cm−2 as a result of the FGA process. This is in contrast to the observed increase in border trap density after FGA from 7.3×1011 cm−27.3×1011 cm−2 to 1.4×1012 cm−21.4×1012 cm−2 in p-type In0.53Ga0.47 As (110) MOSCAPs, which suggest FGA is not as effective in passsivating states close to the valence band edge

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Beyond Silicon MOS : An Electrical Study on Interface and Gate Dielectrics with ac Admittance Techniques

Lin

Vais

Gaur

et al. 2019

Materials Science and Technology

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Recent developments in complimentary metal–oxide semiconductor (CMOS)‐driven compound semiconductors (III–V), Germanium (Ge) and two‐dimensional (2‐D) materials technologies provide new opportunities in advancing the performance envelope of MOS device as well as the relevant electrical characterization techniques. Understanding the electrical characteristics of the metal–oxide–semiconductor (MOS) interface and defects through capacitance‐voltage (CV), conductance voltage (GV) and ac‐transconductance responses can lead to more realistic assessments of the oxide–semiconductor material systems and accurate performance predictions. In this article, interface trap density distributions D it ( E ) of Germanium, III–V compound semiconductors are characterized and/or illustrated. The characterization, modeling and temperature dependence of oxide border traps are presented as the defect study probes beyond the oxide–semiconductor interface. Finally, an investigation on 2‐D materials based MOS devices extends the ac admittance techniques beyond conventional semiconductor materials.

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A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

Abstract: . The latter, cause an almost step-like increase in transconductance at 1-10 GHz. This demonstrates the importance of high frequency characterization of high-κ dielectrics in III-V MOSFETs.

Cited by 81 publications

References 14 publications

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

Multi-frequency inversion-charge pumping for charge separation and mobility analysis in high-k/InGaAs metal-oxide-semiconductor field-effect transistors

The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors

Beyond Silicon MOS : An Electrical Study on Interface and Gate Dielectrics with ac Admittance Techniques

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