A high level SoC power estimation based on IP modeling

Abstract

Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is estimated after RTL synthesis. We propose in this article a methodology based on measurements which allows to model the application power consumption with architectural and algorithmic parameters. So, the modeled applications can be added in a library in order to help the system designer to determine early in the design flow the best adequacy between high performances and low power consumption.

Dynamic power estimation based on switching activity propagation

“…In the work of [4], a methodology was proposed, based on real measurements, which allows designers to model power consumption with architectural and algorithmic parameters. Design reuse is a key advantage of this method.…”

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

“…This is mainly due to the fairly accurate power models made at layout level. Power models can also be developed for IP components and processors using different modelling techniques such as FLPA or ILPA [32]- [35]. In [36], FPGA-based power models for DSP-oriented designs have been presented.…”

“…In fact, such techniques have been widely studied and aim at extrapolating power as a function of parameters of interest [32]- [36], [38]. In our case, analytical power models have been developed using curve fitting and linear regressions.…”

An efficient hybrid power modeling approach for accurate gate-level power estimation

“…Mostly, power models are created by computing power consumption at different levels of abstraction [1]. However, in some cases the assessment is not completely reliable as the estimation methodology does not fit the IP characteristics and a detailed information of power consumption per component cannot not be obtained.…”