A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

An FPGA Implementation Method based on Distributed-register Architectures

“…3 for a benchmark application DCT (48 operation nodes, not including conditional branches). In this implementation, we have assumed 4 adders and 4 multipliers as the FU constraint [2]. In order to show the validity of DR-based circuits, we have also implemented its SR-based circuit on the FPGA chip * 5 .…”

“…In this paper, we have proposed an FPGA implementation method utilizing HLS techniques for DR architectures and applied it to a DR-based circuit of DCT application designed by the approach in Ref. [2]. As the contributions of this paper, we have presented the method to practically implement DR-based circuits including interface circuits on FPGA chips.…”

“…3. In this paper, we use the method [2] for DR-based circuit designs where HLS techniques are effectively utilized. We also use Xilinx Vivado Design Suite 2014.2 [6] for FPGA implementation.…”

“…Several methods for DR-based circuit designs have been proposed [1], [2], where high-level synthesis (HLS) techniques are effectively utilized. These methods introduce, in HLS stage, floorplanning of modules which consist of FUs and local registers, which enables estimation and handling of interconnection delays in HLS.…”

“…From this reason, we propose, in this paper, an FPGA implementation method based on DR architectures and apply it to a DR-based circuit designed by the approach in Ref. [2]. The contributions of this paper are summarized as follows:…”