A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs

Cui, Ke; Ren, Zhongjie; Li, Xiangyu; Liu, Zong-Kai; Zhu, Rihong

doi:10.1109/tns.2016.2632168

Cited by 45 publications

(35 citation statements)

References 18 publications

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“…Obviously, the DNL of such TDCs avoids the bad influence of the uneven bin granularity, since the resolution is determined by the physical length difference of the two ROs but not the bin widths of the used carry chains as in the TDL form. Much reduced DNL has been observed in [17]. However, since the ROs are not compensated and stabilized during the time measurement, the oscillation number cannot be set too large to assure small precision RMS which means that tradeoff between the resolution and the precision should be carefully considered and made by the designers.…”

Section: A Carry Chain Ro-based Tdc Structurementioning

confidence: 99%

“…2) key design point for the fine time interpolator module: The fine time interpolator module contains two structuresymmetric ROs built from the carry chains. The structural similarity is obtained by utilizing the partition based twostep construction method proposed in [17]. The complete oscillation period of the RO is composed of three parts: τ p1 caused by the carry chain (the path encompassed by the dotted rectangle), τ p2 caused by the connection path between the end of the carry chain and the pulse reshaping module (the bold line), and τ p3 caused by all the remaining logic units and paths in the RO as shown in Fig.4.…”

Section: B Key Design Pointsmentioning

confidence: 99%

“…Recently, we proposed a new ring-oscillator-based (RObased) TDC structure by organizing the carry chains in a Vernier loop style [17]. A specific construction method to set up two ROs with very little period difference was fully illustrated.…”

Section: Introductionmentioning

confidence: 99%

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Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

Cui

Liu

et al. 2017

IEEE Trans. Radiat. Plasma Med. Sci.

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Abstract-For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps~37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB~0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB~0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

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Section: A Carry Chain Ro-based Tdc Structurementioning

confidence: 99%

Section: B Key Design Pointsmentioning

confidence: 99%

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Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

Cui

Liu

et al. 2017

IEEE Trans. Radiat. Plasma Med. Sci.

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“…7 TDCs have been implemented in the analog domain by using application-specific integrated circuits (ASICs) capable of providing high time resolution. [17][18][19][20] However, a lack of uniformity in the delay cell of FPGA-based TDC implementations lowers the time resolution. Thus, numerous FPGA-based TDCs have been proposed recently.…”

Section: Introductionmentioning

confidence: 99%

“…Thus, numerous FPGA-based TDCs have been proposed recently. [17][18][19][20] However, a lack of uniformity in the delay cell of FPGA-based TDC implementations lowers the time resolution. Thus, numerous studies have attempted to deal with the nonuniformity in the delay cell of FPGA platforms by using calibration circuits.…”

Section: Introductionmentioning

confidence: 99%

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

Chen

2018

Circuit Theory & Apps

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In this study, we propose a robust field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with run-time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four-step finite state machine (FSM) for run-time calibration. We implemented the TDC with the proposed run-time calibration circuit on the Xilinx 65-nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run-time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27 • C to approximately 70 • C indicated that the proposed run-time calibration circuit enhanced the capability of the FPGA-based TDC against temperature effects. The FPGA-based TDC with the proposed run-time calibration FSM provides robust high-resolution performance suited for a range of scientific applications. KEYWORDS differential nonlinearity (DNL), field-programmable gate array (FPGA), run-time calibration, time-to-digital converter (TDC) Int J Circ Theor Appl. 2019;47:19-31.wileyonlinelibrary.com/journal/cta

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FPGA-Based Implementation of Time-To-Digital Converter

Mangalam¹,

Meishree²,

Mageshwari³

et al. 2023

Lecture Notes in Networks and Systems

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A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs

Cited by 45 publications

References 18 publications

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

Toward Implementing Multichannels, Ring-Oscillator-Based, Vernier Time-to-Digital Converter in FPGAs: Key Design Points and Construction Method

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

FPGA-Based Implementation of Time-To-Digital Converter

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