A High-Linearity Vernier Time-to-Digital Converter on FPGAs With Improved Resolution Using Bidirectional-Operating Vernier Delay Lines

Cui, Ke; Li, Xiangyu

doi:10.1109/tim.2019.2959423

Cited by 29 publications

(23 citation statements)

References 28 publications

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“…A TDC architecture that employs the carry chains in a dissimilar method reasonably so as to improve this long-standing issue is suggested [7]. The independent two carry chains functioning as the delay lines for the fine time interpolation are structured in a ring-oscillator-dependent Vernier style and a time variation among them is adjusted finely through conveying dissimilar numbers of essential delay cells.…”

Section: Related Workmentioning

confidence: 99%

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Multichannel Ring Oscillator Based Time Interval Measurement with Binwidth Calibration

latha¹,

Sivakumar²,

Y.V³

2021

DSA

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Time to digital converters (TDC) is used to calculate a time interval between two occurrences in digital domain. They are used in the field of communication for laser range finding, Nuclear reactor and calibration tools in measuring techniques. Most industrial applications use Application Specific Integrated Circuits (ASICs) for time interval measurement. But, with the increasing technological trends, there arises a need for high performance, low nonlinearity measurement devices with better flexibility and resolution. The proposed work is implementation of Multichannel Time interval measurement using the ring oscillator approach along with bin-width calibration using Xilinx 14.1 ISE and Spartan-6 Field Programmable Gate Array (FPGA). In Multichannel architecture the channels influence each other during the operation and minimizes the linearity error. In order to compensate for process, voltage and temperature fluctuations and changes resulting from the ionizers, the ring oscillator is positioned within Phase Locked Loop (PLL). It also decreases the complexity of the circuit by minimizing the number of delay elements. Bin by bin calibration is used to reduce the bin widths Variations. A very large number of events need to be obtained to maximize the calibration time if high-precision calibration is needed in order to minimize statistical fluctuation. Calibration monitors and controls errors or uncertainties to an appropriate level for the calculation procedure. As a consequence, the relative phases of two input clock signals are highly precise. Therefore, precision time measurements with low cost and good efficiency are carried out in our implementation.

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Section: Related Workmentioning

confidence: 99%

“…The Gated Ring Oscillator (GRO) based architecture [1] with low power consumption and robust with self-calibrating TDC is proposed. The VDL based TDC [7] shows better performance and linearity. [10] gives high resolution and better flexibility.…”

Section: Introductionmentioning

confidence: 99%

Multichannel Ring Oscillator Based Time Interval Measurement with Binwidth Calibration

latha¹,

Sivakumar²,

Y.V³

2021

DSA

View full text Add to dashboard Cite

show abstract

“…However, for TDCs with an extended measurement range (> 500 ns), onboard histogramming modules cost significant BRAM resources, not suitable for multichannel TDC designs. Therefore, many previously reported TDCs with long measurement ranges can only post-process data in PCs [35], [37], [41], [42].…”

Section: Introductionmentioning

confidence: 99%

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Xie

Wang

Chen

et al. 2022

IEEE Trans. Ind. Electron.

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This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

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“…The rest of this section will mainly discuss about the prior arts on fine TDC developments. There are multiple prior techniques employed in the implementation of fine FPGA TDCs, such as large-scale phase matrix (LSPM) [12][13], wave union [14][15], Vernier delay lines [16][17] and tapped delay line (TDL). Several approaches of TDL technique have been demonstrated in prior arts, such as TDL utilizing uniform taps [18] and non-uniform taps [19].…”

Section: Introductionmentioning

confidence: 99%

“…One loop is controlled by the pulse input and counted by the other controlled by the clocksynchronized pulse input to generate the output code. Unlike in TDL structures, the delay line loops used in Vernier structures do not generate ultra-wide bins, and consequently, a more accurate clock division can be achieved with lower linearity errors, as shown with DNL of -0.20 LSB to 0.25 LSB and INL of 0.03 LSB to 0.82 LSB in prior arts [16]. One of the drawbacks of the technique is the requirement to circulate a large number of cycles for each measurement [16].…”

Section: Introductionmentioning

confidence: 99%

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

et al. 2022

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A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as -1.470 -1.676 LSB for Stratix IV to demonstrate its excellent linearity.INDEX TERMS Field programmable gate array (FPGA), merged TDL, phase selection, phase sorting, phase wrapping, time-to-digital converter.

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A High-Linearity Vernier Time-to-Digital Converter on FPGAs With Improved Resolution Using Bidirectional-Operating Vernier Delay Lines

Cited by 29 publications

References 28 publications

Multichannel Ring Oscillator Based Time Interval Measurement with Binwidth Calibration

Multichannel Ring Oscillator Based Time Interval Measurement with Binwidth Calibration

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

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