A high performance 0.13 μm SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

Sleight, J.W.; Varekamp, P.; Lustig, N.; Adkisson, J.; Allen, Andrew J.; Bula, O.; Chen, X.; Chou, Tzu-Jen; Chu, Wei; Fitzsimmons, J.; Gabor, Allen H.; Gates, S. M.; Jamison, P.; Khare, Mukesh; Lai, Liangzhen; Lee, J.; Narasimha, S.; Ellis-Monaghan, John; Peterson, K.; Rauch, S.E.; Shukla, Shubham; Smeys, P.; Su, Tai-Chi; Quinlan, Jennifer J.; Vayshenker, A.; Ward, Billy; Womack, S.; Barth, E.; Biery, G.; Davis, Charles R.; Ferguson, R. S.; Goldblatt, R.; Leobandung, E.; Weiser, J.; Yang, Inchul; Agnello, P.

doi:10.1109/iedm.2001.979476

Cited by 5 publications

(4 citation statements)

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“…Going to thinner films has a noticeable impact on device performance. This is shown in Figure 10, based on the results of our secondgeneration 0.13-m SOI CMOS, where the ring performance improves as the film thickness is reduced [20].…”

Section: Figurementioning

confidence: 93%

“…Measured impact of SOI film thickness on total C J and ring performance. Reproduced with permission from [20]…”

Section: Figure 10mentioning

confidence: 99%

“…As we move forward, SOI CMOS technology development is completed for the 0.13-m generation [6,20] and has been initiated for the 0.1-m generation [7,27]. These technologies are simply the highest-performance CMOS in production.…”

Section: Futurementioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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Section: Figurementioning

confidence: 93%

“…Measured impact of SOI film thickness on total C J and ring performance. Reproduced with permission from [20]…”

Section: Figure 10mentioning

confidence: 99%

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SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

174

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“…Commercial interest in SOI is increasing at least in part due to its reduced parasitic capacitances and therefore potential for high-speed operation [5]. On the other hand, just as in conventional CMOS [6], any reduction in node capacitance has the potential to lower the charge needed to cause an upset, thereby increasing the sensitivity of circuits to radiation induced disturbances.…”

Section: Introductionmentioning

confidence: 99%

A Radiation Hard Lut Block with Auto-Scrubbing

Haque

Beckett

2011

2011 21st International Conference on Field Programmable Logic and Applications

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We present a Silicon-on-Insulator based Look-up Table and configuration memory for application within a radiation hard reconfigurable system. The configuration storage includes a non-volatile EEPROM built using a standard single polysilicon Silicon on Insulator CMOS process linked to a Schmitt sense amplifier and transmission gate LUT structure. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self correcting, or "autoscrubbing" behavior. While the SOI EEPROM and Schmitt exhibit high intrinsic resistance to radiation induced errors, it is still possible for a sequence of two particle strikes to cause the configuration value to be lost. We undertake a preliminary analysis of the Single Event error Rate (SER) performance that results from this behavior.

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