A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation

Bohr, M.; Ahmed, Shibly; Brigham, L.; Chau, R.; Gasser, R.; Green, R.; Hargrove, W.; Lee, E.; Natter, R.; Thompson, Scott E.; Weldon, K.; Yang, Shengqi

doi:10.1109/iedm.1994.383414

Cited by 32 publications

(14 citation statements)

References 7 publications

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“…11 Low values for CV/I are preferred. Figure 6 shows the very good fit (R-squaredϭ0.99) between these simulated data versus a simple linear model of the delay for all these data points:…”

Section: Simulation Resultsmentioning

confidence: 96%

Metal–oxide–semiconductor field-effect transistor junction requirements

Duane

Lynch

1998

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Articles you may be interested inSample size requirements for estimating effective dose from computed tomography using solid-state metaloxide-semiconductor field-effect transistor dosimetry Med. Phys. 41, 042102 (2014); 10.1118/1.4868693Mechanism of random telegraph noise in junction leakage current of metal-oxide-semiconductor field-effect transistor Electron holography analysis of a shallow junction for planar-bulk metal-oxide-semiconductor field-effect transistors approaching the scaling limit Influence of dislocations in strained Si ∕ relaxed SiGe layers on n + ∕ p -junctions in a metal-oxide-semiconductor field-effect transistor technology Secondary ion mass spectrometry characterization of source/drain junctions for strained silicon channel metal-oxide-semiconductor field-effect transistorsThe detailed requirements for shallow junctions for deep sub-micron metal-oxide-semiconductor field-effect transistors are reviewed and explained. The National Technology Roadmap for Semiconductors lists the concentration and depth requirements for the next several generations of technology, but does not provide detailed explanation of the electrical requirements that drive these physical junction characteristics. There are actually many more constraints on junction formation in an integrated complimentary metal-oxide-semiconductor flow, e.g., the effect of the junction formation on the channel region, which can include poly depletion, boron penetration, and reverse short channel effects. The guidelines presented here should be useful to researchers developing ultrashallow junction processes or measurement techniques.

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“…11 Low values for CV/I are preferred. Figure 6 shows the very good fit (R-squaredϭ0.99) between these simulated data versus a simple linear model of the delay for all these data points:…”

Section: Simulation Resultsmentioning

confidence: 96%

Metal–oxide–semiconductor field-effect transistor junction requirements

Duane

Lynch

1998

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…1) The Single-Event Upset (SEU) critical charge ( ) of Static Random-Access Memories (SRAMs) constantly [156], [157], [218]- [227] and Bulk-Fin [158], [159], [228] devices. Note that the hump at = 90 nm represents the result of mobility enhancement due to strain engineering and other techniques.…”

Section: Discussionmentioning

confidence: 99%

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

Kobayashi

2021

IEEE Trans. Nucl. Sci.

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“…The replacement of local oxidation with shallow trench isolation for the 0.35pm generation in 1994 [3] left ion implantation and diffusion as the most critical processing steps. Detailed physical modeling of damage formation during ion implantation, dopant-defect clustering in the early stages of annealing, and subsequent cluster dissolution and transient enhanced diffusion, were essential to understand the annealing behavior.…”

Section: Il Entering the Nanotechnology Eramentioning

confidence: 99%

TCAD Challenges in the Nanotechnology Era

Giles

2005

2005 International Conference on Simulation of Semiconductor Processes and Devices

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TCAD process and device modeling has become an essential component of advanced technology development, delivering physical insight into processes and device operation and enabling development and optimization of technology flows. This paper highlights emerging challenges in extending these capabilities into the nanotechnology era, and the opportunities for a hierarchical, physically-based modeling approach to impact the direction of nanotechnology development.

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A high performance 0.35 μm logic technology for 3.3 V and 2.5 V operation

Cited by 32 publications

References 7 publications

Metal–oxide–semiconductor field-effect transistor junction requirements

Metal–oxide–semiconductor field-effect transistor junction requirements

Scaling Trends of Digital Single-Event Effects: A Survey of SEU and SET Parameters and Comparison With Transistor Performance

TCAD Challenges in the Nanotechnology Era

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