A high performance charge plasma PN-Schottky collector transistor on silicon-on-insulator

Abstract

In this paper, we propose a new high performance PN-Schottky collector (PN-SC) lateral bipolar junction transistor (BJT) on silicon-on-insulator (SOI). The proposed device addresses the problem of poor speed of conventional lateral PNP-BJT device by using a Schottky collector. Further, it does not use the conventional ways of ion implantation/diffusion to realize n and p type doped region. However, it uses metal electrodes of different work functions to create n and p type charge plasma in an undoped silicon film. The simulation study of the proposed lateral PN-SC bipolar charge plasma transistor on SOI (PN-SC-BCPT) device has shown a significant improvement in current gain (β), cutoff frequency (f T ) and switching performance in comparison to conventional PNP-BJT and PNP-bipolar charge plasma transistor (PNP-BCPT) devices. A significantly high β is obtained in the proposed PN-SC-BCPT (∼2100) in comparison to PNP-BCPT (∼1450) and the conventional BJT (∼9) devices, respectively. It has been observed that there is 89.56% and 153.5% increase in f T for the proposed PN-SC-BCPT device (2.18 GHz) in comparison to conventional PNP-BJT (1.15 GHz) and PNP-BCPT (0.86 GHz) devices, respectively. Further, reductions of 24.6% and 15.4% in switching ON-delay and 66% and 30.76% in switching OFF-delay have been achieved in the proposed device based inverters in comparison to PNP-BCPT and the conventional BJT devices based inverters, respectively. Furthermore, the proposed device does not face doping related issues and the requirement of high temperature processing is absent.

Design and simulation of a high performance dopingless p-tunnel field effect transistor

“…Since the device does not use conventional ion implantation or diffusion for realizing doped regions, it is free from random dopant fluctuations issues [4][5][6]. Further, there is no need for a high temperature annealing process and no need of abrupt junctions; it can be processed at low temperatures [7][8][9][10][11][12]. Furthermore, the subthreshold slope (SS) of the proposed device is lower than the 60 mV/dec limit; therefore, it can be scaled further and the supply voltage can also be scaled further without performance loss.…”

Metal controlled nanoscaled dopingless MOSFET on selective/partial buried oxide

“…The doping‐related issues such as RDF can be addressed by realising the doped regions in devices not by the chemical doping techniques, but by using a charge plasma (CP) concept [12–15, 16]. The CP concept uses different metal work functions (W.Fs) for the realisation of differently doped regions in nanoscaled devices.…”

Comparative study of InGaN and InGaAs based dopingless TFET with different gate engineering techniques

“…Moreover, many authors have done the temperature and mathematical model based analysis for different structures of TFET [12][13][14][15]. In this paper, the dopingless TFET with different channel materials using charge plasma concept [16,17] is investigated, which makes it free from random doping fluctuations [18]. Till now, charge plasma based diode [17] is only fabricated, where doping is created in silicon bar by depositing the metal electrodes of the required work-functions.…”