A high-performance, low-power linear algebra core

Abstract

Achieving high-performance while reducing power consumption is the key question as technology scaling is reaching its limits. It is well-accepted that application-specific custom hardware can achieve orders of magnitude improvements in efficiency. The question is whether such efficiency can be maintained while providing enough flexibility to implement a broad class of operations. In this paper, we aim to answer this question for the domain of matrix computations. We propose a design of a novel linear algebra processor and demonstrate that it can achieve orders of magnitude improvements in efficiency for matrix-matrix multiplication, an operation that is indicative for a broad class of matrix computations. A feasibility study shows that 46 double-and 113 single-precision GFLOPS/W can be achieved in 13.6 and 11 GFLOPS/mm 2 , respectively with current components and standard 45nm technology.

Floating Point Architecture Extensions for Optimized Matrix Factorization

“…For the vector norm, we use the original algorithm as the baseline, which requires 257, 769 or 1025 operations per corresponding vector norm of size k = 64, 128, 256. Since our implementation will result in an effective reduction in the number of actually required computations, the extensions have higher GOPS/W than what is reported as peak GFLOPS/W for the LAC in [5].…”

“…The microarchitecture of the Linear Algebra Core (LAC) is illustrated in Figure 1. LAC achieves orders of magnitude better efficiency in power and area consumption compared to conventional general purpose architectures [5]. It is specifically optimized to perform rank-1 updates that form the inner kernels of parallel matrix multiplication.…”

“…Details of the basic PE and core-level implementation of a LAC in 45nm bulk CMOS technology are reported in [5]. For floating-point units, we use the power and area data from [28].…”

“…This exposes the limitations in current architectures that cause additional complexities. We start from a minimal-hardware Linear Algebra Processor (LAP) [5] that was designed for GEMM and other similar matrix-matrix operations (level-3 BLAS [6]). Then, we add minimal, necessary but sufficient logic to avoid the need for running complex computations on a general purpose core.…”

Transpose-free variable-size FFT accelerator based on-chip SRAM

“…FFT algorithms typically perform poorly on general-purpose platforms, because the power-of-two strides of the FFT algorithm interact poorly with set-associative cache, set-associative address translation mechanism, and power-of-banked memory subsystem [1]. FFTW, developed by M. Frigo et al, is known as the fastest software implementation of the FFT algorithm.…”