A high-performance low-power near-Vt RRAM-based FPGA

Abstract

Abstract-The routing architecture, heavily using programmable switches, dominates the area, delay and power of Field Programmable Gate Arrays (FPGAs). Resistive Random Access Memories (RRAMs) enable high-performance routing architectures through the replacement of Static Random Access Memory (SRAM)-based programming switches. Exploiting the very low on-resistance state achievable by RRAMs, RRAM-based routing multiplexers can be used to significantly reduce the FPGA routing delays. In addition, RRAM-based routing architectures are less sensitive to supply voltage reductions and show promises in low-power FPGA designs. In this paper, we propose a nearVt low-power RRAM-based FPGA where both delay and power reductions are achieved. Experimental results demonstrate that a near-Vt RRAM-based FPGA design leads to a 15% area shrink, a 10% delay reduction, and a 65% power improvement, compared to a conventional FPGA design for a given technology node. To achieve low on-resistance values, RRAMs typically require high programming currents. In other word, they need relatively large programming transistors, potentially resulting in area, delay and power inefficiencies. We also present a design methodology to properly size the programming transistors of RRAMs in order to further improve the area-efficiency. Experimental results show that a correct programming transistor sizing strategy contributes to further 18% area and 2% delay shrink, compared to the initial near-Vt RRAM-based FPGA.

Accurate power analysis for near-V<inf>t</inf> RRAM-based FPGA

“…Compared to SRAM-based FPGA, RRAM-based FPGA obtains performance gain thanks to the RRAM-based routing elements that typically provide up to 75% less resistances than standard transistors. Additionally, the performance of RRAM-based circuits is not sensitive to the supply voltages, unlike SRAM-based counterparts, and the programming transistor sizing technique can further reduce the area, delay of RRAM-based circuits [6]. At nominal working voltage, previous works [1]- [5] predict 7% − 15% area shrinks, 10% − 58% performance gains, and 20% − 55% power reductions, compared to SRAM-based FPGAs.…”

“…When used to propagate signals, RRAMs can reduce up to 75% resistance in datapaths compared to standard transistors, leading to a performance gain from 10% to 55% [4]. Previous works [1]- [6] address that RRAM-based FPGAs reduce 20 − 65% power consumption. Despite the strong interest of RRAM-based FPGAs for power reduction, there is very limited work on studying precisely their power sources.…”

“…Thanks to their Back-End-of-Line (BEoL) integration capabilities, RRAMs do not occupy transistor area as SRAMs do, contributing to 7 − 15% area shrink [2]. More advanced RRAM-based FPGA architectures employ RRAMs as high-performance programmable switches [4]- [6]. When used to propagate signals, RRAMs can reduce up to 75% resistance in datapaths compared to standard transistors, leading to a performance gain from 10% to 55% [4].…”

“…Resistive Random Access Memory (RRAM) technology recently motivated intensive research efforts in exploring novel FPGA architectures [1]- [6]. RRAMs can bring to FPGA technologies both non-volatility and performance enhancements.…”

Optimization opportunities in RRAM-based FPGA architectures

“…Previous works [1]- [6] focus on replacing Static Random Access Memory (SRAM)-based multiplexers in the classical FPGA architectures with RRAM-based multiplexers. Since RRAM-based multiplexers are naturally more delay-efficient than SRAM-based multiplexers, RRAM-based FPGAs can achieve a 7%-15% gain in area, a 45%-58% reduction in delay and a 20%-58% reduction in power, when compared to SRAM-based FPGAs [1]- [4]. However, very limited works focus on the architectural repercussions of this technology and study novel RRAM-based architectures that can fully unlock the potential of RRAM-based multiplexers.…”