A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

Song, Yu; Ignjatović, Željko

doi:10.1109/tcsii.2011.2158754

Cited by 9 publications

(6 citation statements)

References 9 publications

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“…One way to achieve this is to shift the upgrade signal outside the baseband of the legacy ONU receivers using subcarrier modulation. Although theoretically possible, this approach suffers from the cost and complexity of radio frequency components [4]. Another way is to shape the spectrum of the upgrade signal using a specific high frequency line coding [5].…”

Section: Resultsmentioning

confidence: 99%

“…The integer‐N PLL frequency synthesizer is considered to be well understood and less complicated to design. Numerous designs of 2.4 GHz PLLs are found in standard CMOS process and performed much growth in recent years . In , the authors adopt dynamic current‐matching charge pump (CP) and gate‐offset linearization technique to improve the phase noise and spur performance.…”

Section: Introductionmentioning

confidence: 99%

“…A low voltage design to reduce power consumption is published and attractive, but with a bigger chip area of 1.68 mm 2 . Literature uses a switched capacitor (SC) loop filter (LF) to reduce on‐chip capacitors area, but the active SC LFs will introduce more power consumption and noise, which will lead to a poor phase noise performance.…”

Section: Introductionmentioning

confidence: 99%

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A 2.4‐GHz frequency synthesizer with a discrete‐time sample‐hold‐reset loops filter

Huang

Lai

Yang

2014

Micro & Optical Tech Letters

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A 2.4‐GHz integer‐N frequency synthesizer is implemented in TSMC 0.18‐μm CMOS process. This article proposes a charge pump (CP) linearization technique and uses a current‐switching differential Colpitts VCO to lower the phase noise and an averaged varactor circuit to increase the linearity of the VCO tuning range. A three phase sample‐hold‐reset loop filter that isolates the CP output node from the VCO tuning node, which improves synthesizer spur performance, minimizes phase noise and reduces on‐chip capacitors area. At 1.8 V supply voltage, measured results of the proposed prototype achieves a wide tuning range from 2.24 to 2.42 GHz, corresponding to 7.7%, a phase noise of −114.76 dBc/Hz at 1 MHz offset frequency from 2.4 GHz, a power consumption of 13.6 mW and an output power of −8.43 dBm. Including pads, the chip area only occupies 0.849 (0.899 × 0.944) mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2591–2598, 2014

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 2.4‐GHz frequency synthesizer with a discrete‐time sample‐hold‐reset loops filter

Huang

Lai

Yang

2014

Micro & Optical Tech Letters

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“…15.4a specification allows transferring this information with low-rate wireless personal area networks (LR-WPANs) [1]. Many designs of 2.4 GHz PLLs are shown in CMOS processing standard and performed much growth in recent years [2]- [5]. The designers support dynamic currentmatching charge pump and gate-offset linearization technique to improve the phase noise and spur performance in [2].…”

Section: Introductionmentioning

confidence: 99%

“…This method is published and attractive such as chip area of 1.68 mm 2 [4]. Literature [5] purposes a switched capacitor (SC) loop filter to reduce onchipset capacitors area. Unfortunately, the active SC loop filters will lead more noise and power consumption, which will to introduce a poor phase noise performance.…”

Section: Introductionmentioning

confidence: 99%

Frequency synthesizer with filter to signal detection for health care wireless network applications

Lai

Huang

2014

Proceedings of 2nd International Conference on Information Technology and Electronic Commerce

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A 2.4 GHz integer-N frequency synthesizer is purposed in tsmc 0.18-μm CMOS process. The purposed design can be used for the IEEE 802.15.4a unlicensed ultra-wideband healthcare applications such as body sensor network to wireless connect with computer network. Electrocardiogram (ECG) is the important physiological parameters in human body. Through monitoring and analyzing ECG, the current-switching differential Colpitts VCO by charge pump linearization technique can know the health condition of human body and achieve the purpose of prevention and diagnosis for diseases accordingly. In this paper, a solution of this design with a discrete-time sample-hold-reset loop filter build in human body for monitoring ECG signal detection is purposed.

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Design of a high‐performance advanced phase locked loop with high stability external loop filter

Kasilingam

Balaiyah

Nuagah

et al. 2022

IET Circuits, Devices & Syst

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For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase‐frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage‐controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase‐frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage‐controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed‐forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide‐by‐47 and divide‐by‐48) that lacks a few extra flip‐flops which save considerable power and improves the frequency difficulties of the multi‐band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1‐μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS‐based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

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A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

Cited by 9 publications

References 9 publications

A 2.4‐GHz frequency synthesizer with a discrete‐time sample‐hold‐reset loops filter

A 2.4‐GHz frequency synthesizer with a discrete‐time sample‐hold‐reset loops filter

Frequency synthesizer with filter to signal detection for health care wireless network applications

Design of a high‐performance advanced phase locked loop with high stability external loop filter

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