A high performance processor architecture for multimedia applications

Khan, Sohaib; Rashid, Muhammad; Javaid, Faraz

doi:10.1016/j.compeleceng.2017.09.027

Cited by 9 publications

(6 citation statements)

References 15 publications

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“…Besides, studies have been conducted on FPGA-based VLIW design. A 90-and 45-nm sub-word parallelism RISC architecture with various sub-word-sizes [7] is proposed to obtain the performance comparable with the DSP core TMS320C64X [8]. An adaptable VLIW, whose main parameters are reconfigured at design time [9], is built into the 32-bit VEX ISA [10] to operate up to 174.89 MHz.…”

Section: Related Workmentioning

confidence: 99%

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

2020

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This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA). Base integer RV32I and extension instruction sets, including RV32M, RV32F, and RV32D, are selected to implement our VLIW hardware. The proposed architecture packs up eight 32-bit instruction flows, each of which performs fixed operational functions to create a 256-bit long instruction format. However, one obstacle of studying new ISAs, similar to RISC-V, to design VLIW microprocessors is the lack of dedicated compilers. Developing an architecture-specific compiler is really challenging. An instruction scheduler is integrated to dynamically schedule independent instructions into the VLIW instruction format. This scheduler is used to overcome the lack of a dedicated RISC-V VLIW compiler and leverage the available RISC-V GNU toolchain. Unlike conventional VLIWs, our proposed architecture is organized into six main stages, namely, fetch, instruction scheduler, decode, execute, data memory, and writeback. The complete design is verified, synthesized, and implemented on a Xilinx Virtex-6 (xc6vlx240t-1-ff1156). Maximum synthesis frequency reaches 83.739 MHz. The proposed RISC-V-based VLIW architecture obtains an average instructions per cycle value that outperforms that of existing open-source RISC-V cores. INDEX TERMS very long instruction word (VLIW), RISC-V, microprocessor, dynamic scheduling, fieldprogrammable gate arrays (FPGA)

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Section: Related Workmentioning

confidence: 99%

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

2020

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“…Additionally, a hardware can be complex to support the run-time prediction. In [13], the processor architecture that accommodates a customized instruction for multimedia applications is presented. In this architecture, multiple pixel data are computed in parallel using the instruction.…”

Section: ) Application-specific Designmentioning

confidence: 99%

Adaptive Linear Address Map for Bank Interleaving in DRAMs

et al. 2019

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The conventional linear address map can degrade memory utilization and system performance when an access pattern is not linear. To improve memory system performance, the adaptive bank-interleaved linear address map for a DRAM technology is proposed. In our approach, the addresses are efficiently rearranged using the bank-flipping technique for a given application and a memory configuration. The system can configure the address map based on the bank interleaving metric in the systematic way when an application is invoked. Considering image processing applications, the algorithm, the analysis, the design, and the evaluation of the proposed address map are presented. The experimental results show that the presented method can effectively improve the performance with a moderate hardware cost.

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“…E P_base = n × CLK P + (I − 1) × CLK P (10) As far as additional time slots due to hazards are concerned, each case needs to be addressed independently. We have mentioned already that each Jump instruction will unconditionally cost an extra time slot.…”

Section: Formulation For Pipmentioning

confidence: 99%

“…The performance limitations of the SCP were addressed in the advanced versions, which were based on multicycle execution of each instruction, and later followed by incorporation of pipelining, in which multiple instructions could be executed in parallel [6]. Since pipelining was supposed to guarantee massive throughputs, it became the de facto architecture for most modern processors [7,8], video coders/decoders [9,10], and crypto systems [11,12], to name a few. Unfortunately, it was completely overlooked that there might be situations in which the older variants, SCP and Multicycle Processors (MCP), could outperform the Pipelined Processors (PiP).…”

Section: Introductionmentioning

confidence: 99%

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

et al. 2019

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Pipelines, in Reduced Instruction Set Computer (RISC) microprocessors, are expected to provide increased throughputs in most cases. However, there are a few instructions, and therefore entire assembly language codes, that execute faster and hazard-free without pipelines. It is usual for the compilers to generate codes from high level description that are more suitable for the underlying hardware to maintain symmetry with respect to performance; this, however, is not always guaranteed. Therefore, instead of trying to optimize the description to suit the processor design, we try to determine the more suitable processor variant for the given code during compile time, and dynamically reconfigure the system accordingly. In doing so, however, we first need to classify each code according to its suitability to a different processor variant. The latter, in turn, gives us confidence in performance symmetry against various types of codes—this is the primary contribution of the proposed work. We first develop mathematical performance models of three conventional microprocessor designs, and propose a symmetry-improving nonlinear optimization method to achieve code-to-design mapping. Our analysis is based on four different architectures and 324,000 different assembly language codes, each with between 10 and 1000 instructions with different percentages of commonly seen instruction types. Our results suggest that in the sub-micron era, where execution time of each instruction is merely in a few nanoseconds, codes accumulating as low as 5% (or above) hazard causing instructions execute more swiftly on processors without pipelines.

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A high performance processor architecture for multimedia applications

Cited by 9 publications

References 15 publications

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

Adaptive Linear Address Map for Bank Interleaving in DRAMs

An Optimization Framework for Codes Classification and Performance Evaluation of RISC Microprocessors

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