Adaptive Linear Address Map for Bank Interleaving in DRAMs

Hur, Jae Young; Rhim, Sang Woo; Lee, Beom Hak; Jang, Wooyoung

doi:10.1109/access.2019.2940351

Cited by 7 publications

(2 citation statements)

References 18 publications

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“…Main memory accesses that target different banks can proceed concurrently [136]. Modern address mapping schemes (e.g., [166][167][168][169][170]) aim to interleave consequently addressed cache blocks across different banks to exploit bank-level parallelism [136,138].…”

Section: Dram Organization and Operationmentioning

confidence: 99%

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

Olgun,

Osseiran,

Yağlıkçı

et al. 2023

2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)

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We introduce ABACuS, a new low-cost hardware-counterbased RowHammer mitigation technique that performance-, energy-, and area-efficiently scales with worsening RowHammer vulnerability. We observe that both benign workloads and RowHammer attacks tend to access DRAM rows with the same row address in multiple DRAM banks at around the same time. Based on this observation, ABACuS's key idea is to use a single shared row activation counter to track activations to the rows with the same row address in all DRAM banks. Unlike stateof-the-art RowHammer mitigation mechanisms that implement a separate row activation counter for each DRAM bank, ABA-CuS implements fewer counters (e.g., only one) to track an equal number of aggressor rows.Our comprehensive evaluations show that ABACuS securely prevents RowHammer bitflips at low performance/energy overhead and low area cost. We compare ABACuS to four state-ofthe-art mitigation mechanisms. At a near-future RowHammer threshold of 1000, ABACuS incurs only 0.58% (0.77%) performance and 1.66% (2.12%) DRAM energy overheads, averaged across 62 single-core (8-core) workloads, requiring only 9.47 KiB of storage per DRAM rank. At the RowHammer threshold of 1000, the best prior low-area-cost mitigation mechanism incurs 1.80% higher average performance overhead than ABACuS, while ABACuS requires 2.50× smaller chip area to implement. At a future RowHammer threshold of 125, ABACuS performs very similarly to (within 0.38% of the performance of) the best prior performance-and energy-efficient RowHammer mitigation mechanism while requiring 22.72× smaller chip area. We also show that ABACuS's performance scales well with the number of DRAM banks. At the RowHammer threshold of 125, ABA-CuS incurs 1.58%, 1.50%, and 2.60% performance overheads for 16-, 32-, and 64-bank systems across all 62 single-core workloads, respectively. ABACuS is freely and openly available at https://github.com/CMU-SAFARI/ABACuS.

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Section: Dram Organization and Operationmentioning

confidence: 99%

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

Olgun,

Osseiran,

Yağlıkçı

et al. 2023

2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental Volume (DSN-S)

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show abstract

“…The physical address 0 × 126F0 is mapped following the BRC scheme. The APT corresponding to this pixel is in the zeroth and first banks, and the DRAM cell in the 49th row and 752th column performs the storage [31].…”

Section: Address and Pixel Transactionmentioning

confidence: 99%

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Wei

Chen

et al. 2021

Electronics

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Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

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CPR: Correlation-based Page Remapping

Namkoong,

Kim

2023

2023 20th International SoC Design Conference (ISOCC)

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Adaptive Linear Address Map for Bank Interleaving in DRAMs

Cited by 7 publications

References 18 publications

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

An Experimental Analysis of RowHammer in HBM2 DRAM Chips

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

CPR: Correlation-based Page Remapping

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