A high-performance sub-0.25 μm CMOS technology with multiple thresholds and copper interconnects

Su, L.T.; Schulz, R.; Adkisson, J.; Beyer, Kevin; Biery, G.; Cote, W.; Crabbé, E.F.; Edelstein, D.; Ellis-Monaghan, John; Eld, E.; Foster, D.; Gehres, R.; Goldblatt, R.; Greco, Nunzio; Guenther, C.; Heidenreich, J.; Herman, J.; Kiesling, D.; Lin, Lei; Lo, Sui-Sang; McKenna, J.; Megivern, C.; Ng, H.; Oberschmidt, James; Ray, A.; Rohrer, Norman J.; Tallman, K.; Wagner, T.; Davari, B.

doi:10.1109/vlsit.1998.689182

Cited by 14 publications

(4 citation statements)

References 2 publications

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“…There are a number of previous studies that have focused on circuit-level only techniques to reduce leakage power. Techniques such as multi-threshold [30,25,17] or multi-supply [27] voltage designs, dynamic-threshold [29] or dynamic-supply [5] voltage designs, and transistor stacking [32], have been used to reduce leakage energy dissipation while maintaining high performance. However, circuit-level techniques that apply leakage reduction ignore application/architectural behavior and circuit utilization.…”

Section: Related Workmentioning

confidence: 99%

“…There are a myriad of circuit techniques to reduce leakage energy dissipation in transistors/circuits (e.g., multi-threshold [30,25,17,28] or multi-supply [27] voltage designs, dynamic threshold [29] or dynamic supply [5] voltage designs, and transistor stacking [32]). These techniques, however, typically impact circuit performance and are only applicable to circuit sections that are not performance-critical [10].…”

Section: Introductionmentioning

confidence: 99%

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An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Yang

Powell²,

Falsafi

et al.

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

162

167

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Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchitectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy in instruction caches (icaches). At the architectural level, we propose the Dynamically ResIzable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-V dd , a mechanism that effectively turns off the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robustly exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64K DRI i-cache reduces on average both the leakage energy-delay product and cache size by 62%, with less than 4% impact on execution time.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Yang

Powell²,

Falsafi

et al.

Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture

162

167

View full text Add to dashboard Cite

show abstract

“…The International Technology Roadmap for Semiconductors [20] predicts a steady scaling of supply voltage with a corresponding decrease in transistor threshold voltage to maintain a 30% improvement in performance every generation. Transistor threshold scaling, in turn, gives rise to a significant amount of leakage energy dissipation due to an exponential increase in subthreshold leakage current even when the transistor is not switching [3], [28], [24], [16], [22], [11], [6]. Borkar [3] estimates a factor of 7.5 increase in leakage current and a five-fold increase in total leakage energy dissipation in every chip generation.…”

mentioning

confidence: 99%

“…There are a myriad of circuit techniques to reduce leakage energy dissipation in transistors/circuits (e.g., multithreshold [26], [22], [16] or multisupply [9], [23] voltage designs, dynamic threshold [25] or dynamic supply [4] voltage designs, transistor stacking [28], and cooling [3]). These techniques, however, typically impact circuit performance and are only applicable to circuit sections that are not performance-critical [10].…”

mentioning

confidence: 99%

Reducing leakage in a high-performance deep-submicron instruction cache

Powell

Yang

Falsafi

et al. 2001

IEEE Trans. VLSI Syst.

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Abstract-Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchitectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy in instruction caches (i-caches). At the architecture level, we propose the Dynamically ResIzable i-cache (DRI i-cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-, a novel mechanism that effectively turns off the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robustly exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64 K DRI i-cache reduces on average both the leakage energy-delay product and cache size by 62%, with less than 4% impact on execution time. Our results also indicate that a wide NMOS dual-gatedtransistor with a charge pump offers the best gating implementation and virtually eliminates leakage energy with minimal increase in an SRAM cell read time area as compared to an i-cache with an aggressively-scaled threshold voltage.

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Introduction

Cao

2011

Integrated Circuits and Systems

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A high-performance sub-0.25 μm CMOS technology with multiple thresholds and copper interconnects

Cited by 14 publications

References 2 publications

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Reducing leakage in a high-performance deep-submicron instruction cache

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