A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation

Kao, Chao-Yang; Wu, Chen-Wei; Lin, Youn-Long

doi:10.1109/tvlsi.2009.2013629

Cited by 31 publications

(23 citation statements)

References 7 publications

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“…Comparing this work with [8], the S&IS uses a lower area, however it uses a larger number of memory bits. Our architecture can also reach real time when processing QFHD videos while [8] can only process 7.5 frames per second in the same resolution.…”

Section: Results and Comparisonsmentioning

confidence: 95%

“…Table 2 also presents comparisons with related works. This work was compared with the works [6], [8], [10], [11], [12], [13] and [14], presented in section 2. Table 2 presents the following parameters: (1) the technology, (2) the maximum operation frequency reached, (3) consumed area, (4) used memory bits, (5) cycles used per block, (6) reached frames per second for Full HD videos, (7) reached frames per second for QFHDvideo and (8) the power consumption.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…An architecture for the fractional ME of the H.264/AVC standard is presented in [8], where the same algorithm of JM Reference Software [9] for high definition videos is used. It also uses multiple block sizes and the used similarity criterion is SATD.…”

Section: Related Workmentioning

confidence: 99%

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Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Sanchez

Agostini

Sampaio

et al. 2012

2012 IEEE International Conference on Multimedia and Expo

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This paper presents the Spread and Iterative Search (S&IS) motion estimation algorithm, which uses a random spread evaluation together with a central iterative evaluation to avoid local minima falls and to increase the image quality for high definition videos. Considering Full HD videos, S&IS reached an average PSNR gain of 1.41dB when compared to Diamond Search (DS), with an increase of about four times in the number of evaluated blocks. When compared to Full Search (FS), the S&IS achieved an average PSNR loss of 1.56 dB, evaluating 73 times less blocks than FS. An efficient architecture for the S&IS algorithm is also presented in this paper.The architecture was designed targeting in real time processing (30 frames per seconds) for QFHD videos (3840×2160 pixels). The architecture was described in VHDL and synthesized for and Altera Stratix 4 FPGA and for ST90nm standard cells technology. Booth syntheses show that the architecture is able to process QFHD frames in real time. The standard cells version is able to reach also a good trade-off among area, memory and power consumption, processing QFHD videos with 62.2 mW.

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Section: Results and Comparisonsmentioning

confidence: 95%

Section: Results and Comparisonsmentioning

confidence: 99%

See 1 more Smart Citation

Spread and Iterative Search: A High Quality Motion Estimation Algorithm for High Definition Videos and Its VLSI Design

Sanchez

Agostini

Sampaio

et al. 2012

2012 IEEE International Conference on Multimedia and Expo

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“…Thus, the expected cycle of the IME operation for an LCU is approximately 4,096 with a marginal PSNR drop of 0.005 dB when the IME of [8] is used. Meanwhile, the FME in [9] uses 16-pixel-width interpolators and can process an MB in 790 cycles, whereas the FME in [10] adopts multiple interpolators and the FME operation time is 631 cycles. The gate counts are 311 K and 321 K for FMEs in [9] and [10], respectively.…”

Section: Hardware Organization For An Hevc Encodermentioning

confidence: 99%

“…Meanwhile, the FME in [9] uses 16-pixel-width interpolators and can process an MB in 790 cycles, whereas the FME in [10] adopts multiple interpolators and the FME operation time is 631 cycles. The gate counts are 311 K and 321 K for FMEs in [9] and [10], respectively. In both FMEs, the mode reduction schemes are not applied to avoid PSNR degradation.…”

Section: Hardware Organization For An Hevc Encodermentioning

confidence: 99%

Reference frame selection in a hardware-based HEVC encoder

Rhee

Lee

2012

IEICE Electron. Express

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The multiple-reference-frame motion estimation (ME) is one of the features to improve the compression efficiency. However, the computational complexity for prediction increases in proportion to the number of reference frames. This paper proposes the reference frame selection algorithm for a hardware-based HEVC encoder. The integer-ME explores multiple reference frames to find the best one and the fractional ME is then performed for the best reference frame which is determined by the IME. Simulation results show that a significant time saving of 74% is achieved with a negligible drop in compression efficiency.

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