A high-precision hardware-efficient radix-2&lt;sup&gt;k&lt;/sup&gt; FFT processor for SAR imaging system

Yang, Chen; Xie, Yizhuang; Chen, He; Ma, Cuimei

doi:10.1587/elex.13.20160903

Cited by 5 publications

(2 citation statements)

References 12 publications

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“…According to the fixed-point quantization error analysis, a 16,384 point, 16-bit FFT co-processor is implemented. It is a typical radix-2 k single-path delay feedback (SDF) pipeline FFT processor based on our previous research [ 40 ]. The processing latency is approximately 16,500 clock cycles or 0.16 ms at a 100 MHz working frequency.…”

Section: Realization Of the Fpga-asic Accelerating Platformmentioning

confidence: 99%

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Yang

Chen

et al. 2017

Sensors

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With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

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Section: Realization Of the Fpga-asic Accelerating Platformmentioning

confidence: 99%

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Yang

Chen

et al. 2017

Sensors

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“…They implemented the model on the Vertex 5 FPGA board and validated the results with MATLAB-based simulation. Hardware efficient and high precision FFT implementation using the radix-2 algorithm for SAR imaging was presented by Yang et al (2016). The radix 2 k algorithm was implemented in the XC6VCX240T FPGA board using an 18-bit pipeline algorithm achieving 47.3 dB signal to quantization noise ratio.…”

Section: Introductionmentioning

confidence: 99%

Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

Mewada

Chaudhari

Patel

et al. 2020

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Purpose Synthetic aperture radar (SAR) imaging is the most computational intensive algorithm and this makes its implementation challenging for real-time application. This paper aims to present the chirp-scaling algorithm (CSA) for real-time SAR applications, using advanced field programmable gate array (FPGA) processor. Design/methodology/approach A chirp signal is generated and compressed using range Doppler algorithm in MATAB for validation. Fast Fourier transform (FFT) and multiplication operations with complex data types are the major units requiring heavy computation. Therefore, hardware acceleration is proposed and implemented on NEON-FPGA processor using NE10 and CEPHES library. Findings The heuristic analysis of the algorithm using timing analysis and resource usage is presented. It has been observed that FFT execution time is reduced by 61% by boosting the performance of the algorithm and speed of multiplication operation has been doubled because of the optimization. Originality/value Very few literatures have presented the FPGA-based SAR imaging implementation, where analysis of windowing technique was a major interest. This is a unique approach to implement the SAR CSA using a hybrid approach of hardware–software integration on Zynq FPGA. The timing analysis propagates that it is suitable to use this model for real-time SAR applications.

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Low Complexity Fused Floating Point FFT Using CSD Arithmetic for OMP CS System

Radhika

Satyaprasad

Rao³

2021

Data Engineering and Communication Technology

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A high-precision hardware-efficient radix-2<sup>k</sup> FFT processor for SAR imaging system

Cited by 5 publications

References 12 publications

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Hardware accelerated range Doppler algorithm for SAR data processing using Zynq processor

Low Complexity Fused Floating Point FFT Using CSD Arithmetic for OMP CS System

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