A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications

Määttä, Kari; Kostamovaara, J.

doi:10.1109/19.744201

Cited by 104 publications

(26 citation statements)

References 26 publications

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“…For instance, in metrological applications, high throughput has the effect of achieving the wanted accuracy in a shorter time, thus improving the speed of a measurement or making it possible to achieve unprecedented accuracies whenever a phenomenon is fast occurring. Similar advantages could be achieved in RADARs, high-energy physics, and time-resolved imaging [4,5].…”

Section: Introductionmentioning

confidence: 73%

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Favi

Charbon

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed architecture, implemented in a 65nm FPGA system, consists of a pipelined interpolating time-to-digital converter (TDC). The TDC comprises a coarse time discriminator and a fine delay line, capable of sustained operation at a clock frequency of 300MHz. A Turbo version of the circuit implements a pipelined interpolating TDC with suppressed dead time to reach a conversion rate of 300MS/s at the expense of a systematic asymmetry that requires fast error correction. The TDCs proposed in this paper can be compensated for process, voltage, and temperature (PVT) variations using a conventional charge pump based feedback or a digital calibration technique. Results demonstrate the suitability of the approach for a variety of applications involving high-precision ultra-fast time discrimination, such as optical lifetime sensing, time-of-flight cameras, high throughput comlinks, RADARs, etc.

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Section: Introductionmentioning

confidence: 73%

A 17ps time-to-digital converter implemented in 65nm FPGA technology

Favi

Charbon

2009

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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“…However, there is an increasing interest nowadays to integrate TDCs in various imaging platforms to replace ADCs for time-resolve biochemical sensing or high speed imaging applications. These applications include: (1) High energy physics [1] or space science instrumentations, where highspeed space imaging of X-ray and other high energy particles is performed; (2) Medical imaging applications using positron emission tomography [2]; (3) Rang finding and 3D imaging using laser radar [3] or single-photon counting [4] technique for time-of-flight measurement. For such applications, TDCs with wide dynamic range and high throughput readout are usually desirable for high performance and high frame rate imaging implementations.…”

Section: Introductionmentioning

confidence: 99%

A 22-bit 110ps time-interpolated Time-to-Digital Converter

Guo

Sonkusale

2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents a 22-bit time-interpolated Timeto-Digital Converter (TDC) with 110ps temporal resolution for biochemical sensing applications, which utilize time-resolve luminescence imaging technique. The TDC achieves wide dynamic range operation by incorporating a hybrid architecture that combines a 14-bit digital counter based coarse TDC and an 8-bit Voltage-Controlled Delay Line (VCDL) based fine TDC. We have proposed and implemented a novel readout algorithm for VCDL operation that achieves high throughput temporal measurement. A prototype chip has been fabricated in a 65nm standard CMOS process and it consumes 2.4mA power from a 1.2V supply. The measurement results on the fabricated TDC demonstrates a Differential Nonlinearity (DNL) of 0.49LSB and an Integral Nonlinearity (INL) or 1.67LSB (1LSB=110ps). The implemented TDC architecture and its fast readout circuit can be readily used in a variety of time-resolved biomedical sensing or high-speed imaging applications that require both wide dynamic range performance and high frame rate implementations.

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“…Time-to-digital converters (TDCs) measure time intervals for various scientific and engineering applications, such as positron emission tomography (PET) scanners, [1][2][3] time-of-flight PET, 4,5 time-of-flight laser radar, 6 and mass spectrometry. Time-to-digital converters (TDCs) measure time intervals for various scientific and engineering applications, such as positron emission tomography (PET) scanners, [1][2][3] time-of-flight PET, 4,5 time-of-flight laser radar, 6 and mass spectrometry.…”

Section: Introductionmentioning

confidence: 99%

“…Time intervals represent the time difference between two trigger signals. Time-to-digital converters (TDCs) measure time intervals for various scientific and engineering applications, such as positron emission tomography (PET) scanners, [1][2][3] time-of-flight PET, 4,5 time-of-flight laser radar, 6 and mass spectrometry. 7 TDCs have been implemented in the analog domain by using application-specific integrated circuits (ASICs) capable of providing high time resolution.…”

Section: Introductionmentioning

confidence: 99%

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

Chen

2018

Circuit Theory & Apps

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In this study, we propose a robust field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with run-time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four-step finite state machine (FSM) for run-time calibration. We implemented the TDC with the proposed run-time calibration circuit on the Xilinx 65-nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run-time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27 • C to approximately 70 • C indicated that the proposed run-time calibration circuit enhanced the capability of the FPGA-based TDC against temperature effects. The FPGA-based TDC with the proposed run-time calibration FSM provides robust high-resolution performance suited for a range of scientific applications. KEYWORDS differential nonlinearity (DNL), field-programmable gate array (FPGA), run-time calibration, time-to-digital converter (TDC) Int J Circ Theor Appl. 2019;47:19-31.wileyonlinelibrary.com/journal/cta

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A high-precision time-to-digital converter for pulsed time-of-flight laser radar applications

Cited by 104 publications

References 26 publications

A 17ps time-to-digital converter implemented in 65nm FPGA technology

A 17ps time-to-digital converter implemented in 65nm FPGA technology

A 22-bit 110ps time-interpolated Time-to-Digital Converter

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

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