A high-PSRR low-power CMOS voltage reference based on weighted VGS difference

Yousefi, Somayeh; Jalali, Mohsen

doi:10.1016/j.aeue.2015.09.019

Cited by 16 publications

(5 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Table I [24,25,26,27,28,29,30] summarizes and compares the design with other recent papers, from which we can see that although the two reference sources designed by DRPST and PRCT in this paper are not dominant in the required input voltage, they not only have great temperature characteristics but also are prominent in PSRR.…”

Section: Resultsmentioning

confidence: 95%

Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

Song

Chai

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

Two novel PSRR characteristic enhancement technologies based on the voltage reference (VR) is presented: Double-reference PSRR stacking technology (DRPST) and Pre-regulated-current technology (PRCT). The above two novel technologies are explained by designing two voltage reference structures. The voltage reference is obtained by a depletion NMOS and an enhancement NMOS. Structure I employs DRPST compared with the traditional Pre-regulated-voltage technology (PRVT) to improve the PSRR. Structure II uses PRCT composed of DRPST and improved Pre-regulated-voltage technology (IPRVT) to improve PSRR. The above two structural reference sources are simulated in standard 0.18 µm CMOS process. When the output reference is 810 mV, the PSRR of VR obtained in Structure I is −140 dB@1 KHz at TT corner with the line sensitivity: LS = 0.023%/V, the temperature coefficients: TC= 4.2 ppm/ • C; The PSRR of the Structure II is −114 dB@1 KHz at TT corner with LS = 0.013%/V, TC = 7.5 ppm/ • C.

show abstract

Section: Resultsmentioning

confidence: 95%

Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

Song

Chai

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…The FOM 2 is defined by considering the performance parameters such as PSRR, temperature coefficient (TC), area, and supply current 51

{FOM}_{2} = \frac{PSRR @ 100 Hz}{TC \times Supply Current \times Area} .

where PSRR @ 100 Hz is the PSRR at frequency of 100 Hz (frequency of 100 Hz is selected for better comparison with the existing voltage references).…”

Section: Simulation Resultsmentioning

confidence: 99%

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Thakur

Pandey

Kumar

2020

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary A high‐order curvature‐compensated subthreshold voltage reference is proposed in this paper. The proposed curvature‐compensated voltage reference consists of two supply‐independent first‐order voltage references and a curvature compensation circuit. The supply‐independent first‐order voltage reference uses a negative feedback loop which improves the line sensitivity and eliminates the demand of operational amplifier, whereas the curvature compensation circuit provides high‐order temperature‐compensated output reference voltage. The proposed curvature‐compensated voltage reference provides an output reference voltage of 118.54 mV with a temperature coefficient of 21.5 ppm/°C over a wide temperature range of −60°C to 120°C. The power supply rejection ratio and line sensitivity are observed as −68.64 dB (for the frequency range of 1 Hz to 100 Hz) and 0.035%/V (for the supply voltage varies from 0.85 V to 2.5 V), respectively. The values of output noise at the frequencies of 1 kHz and 10 kHz without using any capacitive filter are obtained as 179.13 nV/ √ Hz and 123.87 nV/ √ Hz, respectively.

show abstract

“…The main component of the power management circuit is a low-dropout regulator (LDO) used to regulate and stabilize the battery voltage [30]- [32]. A full CMOS voltage reference circuit is utilized to supply the reference voltage required by the LDO [33], and the output voltage of the LDO serves as the driving voltage for the backend circuit. On the left side of the circuit diagram is the full CMOS voltage reference circuit, consisting of seven MOS transistors and three resistors.…”

Section: Chip Design Of the Power Management Readout Circuitmentioning

confidence: 99%

Development of a Flexible Printed Circuit Board-Based Potentiometric Urea Biosensor Combined With Power Management Circuit Chip

Kuo,

Wang,

Hsu

et al. 2023

IEEE Access

View full text Add to dashboard Cite

This study proposes a power management circuit integrated with a readout circuit for measuring urea biosensors. The proposed power management circuit replaces the bulky power supply traditionally used in measurement systems. It operates with only a single 3V button cell for voltage reduction and stabilization. We have designed and manufactured a printed circuit board (PCB) that integrates passive components and power management readout circuit chip for measuring a urea biosensor. A RuO2 thin film was prepared on a flexible printed circuit board (FPCB) through radio frequency (RF) sputtering. To fabricate the urea sensor, we used 3-Aminopropyltriethoxysilane (γ-APTES), glutaraldehyde, and urease. The average sensitivity of the urea sensor was evaluated to be 3.121 (mV/(mg/dL)), with a linearity of 0.994 and a reproducibility of 2.59 %. These results confirm the stability and reliability of the sensor architecture.INDEX TERMS Urea biosensor, power management, flexible printed circuit board (FPCB), full CMOS voltage reference.

show abstract

A high-PSRR low-power CMOS voltage reference based on weighted VGS difference

Cited by 16 publications

References 14 publications

Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

Two novel PSRR enhancement techniques for voltage reference of depletion NMOS

Low temperature coefficient and low line sensitivity subthreshold curvature‐compensated voltage reference

Development of a Flexible Printed Circuit Board-Based Potentiometric Urea Biosensor Combined With Power Management Circuit Chip

Contact Info

Product

Resources

About