A High-Resolution Low-Power Oversampling ADC with Extended-Range for Bio-Sensor Arrays

Agah, Ali; Vleugels, K.; Griffin, P.B.; Ronaghi, Mostafa; Plummer, J.D.; Wooley, B.A.

doi:10.1109/vlsic.2007.4342736

Cited by 25 publications

(18 citation statements)

References 4 publications

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“…An energy-and area-efficient high resolution analog-to-digital converter (ADC) is especially critical for a battery-operated integrated sensor SoC. Sensor applications often involve narrow-band signals with frequencies from DC [1]- [3] up to several hundred Hz [4]- [9], and the ADC should achieve high accuracy even in the presence of DC offset voltage and flicker noise. In addition, often the integrated ADC must be multiplexed among many channels.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, often the integrated ADC must be multiplexed among many channels. In applications requiring hundreds of channels, such as image sensor [10], [11] or bio-potential acquisition [4], [5], [8], [9], the integrated ADCs must be highly efficient in terms of power and chip area SoC.…”

Section: Introductionmentioning

confidence: 99%

“…However, high-order modulators are more prone to instability, and have a reduced non-overloading input range. As an alternative to single-loop modulators, multi-stage noise-shaping (MASH) IADCs [13], [14], and hybrid schemes which incorporate an added Nyquist-rate ADC to perform extended counting [9], [11], [15], [16] were proposed. However, MASH modulators and hybrid extended-counting schemes increase the circuit complexity, and circuit non-idealities may cause severe performance degradation.…”

Section: Introductionmentioning

confidence: 99%

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A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Chen

Zhang

et al. 2015

IEEE J. Solid-State Circuits

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Integrated sensor interface circuits require energy-efficient high-resolution data converters. This paper proposes a twostep incremental A/D converter (IADC) which extends the performance of an th-order IADC close to that of a th-order IADC. The implemented device uses the circuitry of a second-order IADC (IADC2) to achieve close to third-order SNR performance. The proposed circuit does not require very high opamp DC gain; the gain can be as low as 60 dB for 100 dB SNR data conversion. The implemented IADC achieves a measured dynamic range of 99.8 dB, and an SNDR of 91 dB for a maximum input 2.2 V and a bandwidth of 250 Hz. Fabricated in 65 nm CMOS, the IADC's core area is 0.2 mm 2 , and it consumes only 10.7 µW. The measured FoMs are 0.76 pJ/conversion and 173.5 dB, both among the best reported results for IADCs. The measured results verify that the proposed two-step IADC is a more energy-efficient data conversion scheme than conventional high-order IADCs.Index Terms-Analog-to-digital converter (ADC), chopper stabilization, decimation filter, delta sigma ( ), extended-counting, flicker noise elimination, incremental data converters, low power, measurement and instrumentation, multi-stage noise shaping (MASH), multi-step, sensor interface, time-domain signal processing, two step.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Chen

Zhang

et al. 2015

IEEE J. Solid-State Circuits

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“…Since the oversampling ratio is limited to 128 for low power dissipation, a single-loop second-order incremental ADC cannot fulfill the design requirement. To increase the conversion accuracy and at the same time maintain good stability of the loop, the extended counting structure [4], [5] is used. Fig.…”

Section: Design Examplementioning

confidence: 99%

“…The maximum oversampling ratio is also limited by the input signal bandwidth, since low power dissipation is also an important consideration. By using a technique similar to extended counting in a two-step process [4]- [5], the resolution of IDCs can be improved significantly with low-order single-bit modulator and lower oversampling ratio. Calibration is also unnecessary for this architecture.…”

Section: Introductionmentioning

confidence: 99%

Noise-coupled low-power incremental ADCs

Wang

Chen

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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A 0.5-V low power analog front-end for heart-rate detector

Suda

Nishanth

Basak

et al. 2014

Analog Integr Circ Sig Process

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This paper presents a low power analog frontend for heart-rate detector at a supply voltage of 0.5 V in 0.18 lm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8-32 Hz. To digitize the analog signal, a low power second-order RD ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, RD modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 lW from 0.5 V supply.Keywords Low power Á 0.5 V operation Á Second order sigma delta modulator Á Switched opamp Á Switched capacitor filter 1 Introduction

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A High-Resolution Low-Power Oversampling ADC with Extended-Range for Bio-Sensor Arrays

Cited by 25 publications

References 4 publications

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

A Micro-Power Two-Step Incremental Analog-to-Digital Converter

Noise-coupled low-power incremental ADCs

A 0.5-V low power analog front-end for heart-rate detector

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