A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages

Mehrabani, Yavar Safaei; Zareei, Zahra; Khademzadeh, Ahmad

doi:10.1504/ijhpsa.2013.058975

Cited by 6 publications

(5 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The capacitive network performs the voltage division on the input signals and generates a voltage corresponding to the inputs in the V x node. The equation (17) represents the voltage of the V x node, which can be calculated by the superposition theorem (Safaei Mehrabani et al , 2013). …”

Section: Proposed Inexact 4:2 Compressormentioning

confidence: 99%

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

Mehrabani

Bagherizadeh

Shafiabadi

et al. 2019

View full text Add to dashboard Cite

Purpose This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs). Design/methodology/approach To design this cell, the capacitive threshold logic (CTL) has been used. Findings To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others. Originality/value This cell significantly reduces the number of transistors and only consists of NOT gates.

show abstract

Section: Proposed Inexact 4:2 Compressormentioning

confidence: 99%

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

Mehrabani

Bagherizadeh

Shafiabadi

et al. 2019

View full text Add to dashboard Cite

show abstract

“…The Shannon theorem elucidates that the logic expressions are divided into two parts wherein in the first part a variable value is set to logic 1 and multiplied by a multiplier variable and in the next part the original variable that was set to logic 1 is then set to logic 0 followed by its multiplication with complement of multiplier variable. The entire logic can be reduced by reiterating the Shannon's theorem [5]. The generalized Shannon expression of many variables is as depicted below.…”

Section: Shannon's Full Addermentioning

confidence: 99%

“…The f(a0, a1, a2, y, ai, y, an) can be written as the sum of two terms, one with a particular variable (say ai) set to 0, and one with it is set to 1 [5]. f(a0, a1, a2,…., ai,…., an) = ai f(a0, a1, a2,…., 0,…., an) + ai f(a0, a1, a2,…., 1,…., an) [6].…”

Section: Shannon's Full Addermentioning

confidence: 99%

“…The Fig.7 represents the Shannon's full adder network built with CNT devices and simulated in HSPICE environment. In this (n-1) variables are used as control inputs connected to gates of the transistors based on whose value the data available at inputs of the pass transistors are transmitted towards the output [5]. In case of a one bit full adder in Fig.5, the input B and complement of B deliver transmission path to original and complimented variables of A and Carry-in, Thus realizing the sum expression in a simple transistor structure.…”

Section: Shannon's Full Addermentioning

confidence: 99%

“…The speed of computation is major constraint in latest high frequency processors that are designed to be suitable for image and video processing. The rapid growth of portable electronic devices like mobile phones has driven the research towards low power implementation of the digital logic because of the lacuna in battery and power storage technology which has not advanced at the rate of microprocessor integration technology as predicted by Moore [5].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Cntfet Based Novel 14t Adder Cell for Low Power Computation

Ramakrishna¹,

Aswatha²

2017

IJME

View full text Add to dashboard Cite

This paper focuses on the design of a 14 transistor one bit adder cell designed using CNTFET 32nm Technology to address the power and speed issues of high performance computational systems. The performance metrics of the proposed adder cell is compared by benchmarking with conventional full adder design, Transmission gate based full adder and Shannon's expression based full adders using CNTFET technology. The proposed design has lesser delay and very low power consumption. The design embraces Stanford 32nm planar CNTFET library model with a power supply of 1 volt and single walled CNT. Extensive simulation has been carried out on the adder cells considered and the parameters such as power, delay and PDP are investigated. The effect of temperature variation on the power consumption of proposed 14T adder cell is also observed to examine the robustness. The simulation results demonstrate that the proposed adder delivers stable output drivability with substantial diminution in the leakage power.

show abstract