A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters

Wang, Riyan; Li, Kaihang; Zhang, Jianqin; Nie, Bin

doi:10.1109/iwasid.2007.373688

Cited by 19 publications

(5 citation statements)

References 5 publications

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“…High speed, low voltage and power efficiency are the most interesting parameters in the design of comparator [1] [2]. The traditional dynamic latch comparator [6] [8] has single tail current and many stack MOS transistors, which limits the optimization of speed and low voltage operation [5] [6] [7]. The conventional SR latch generates unsynchronized primary and complementary outputs, whereas modified SR latch reduces the delay between primary and complementary outputs and the outputs are more stable than that of conventional SR latch.…”

Section: Introductionmentioning

confidence: 99%

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

Savani

Devashrayee

2015

2015 19th International Symposium on VLSI Design and Test

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this paper presents characterization of low operating voltage, high speed and power efficient comparator used as a basic building block in speed optimized Analog to Digital Converters (ADC), such as flash ADC. Overall performance of any ADC in terms of speed, resolution and power consumption highly depends on the underlying comparator being used. In this paper, better structure of comparator is implemented and analyzed, which is a combination of modified SR latch and sense amplifier. The comparator is built up by preamplifier and positive feedback latch (back-to-back connected inverter) to enhance the speed. The output of latch is given to the modified SR latch, which provides stable output signal compare to that of conventional dynamic latch structure. The implementation is carried out in 90nm technology in Mentor Graphics' IC Studio tool and simulation is done in Eldo tool.

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Section: Introductionmentioning

confidence: 99%

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

Savani

Devashrayee

2015

2015 19th International Symposium on VLSI Design and Test

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“…However, to design circuits for low voltage operations capable of decreasing the dynamic range of the inputs and the corresponding differential process [ 2 , 14 ], the power dissipations in rail-to-rail operations are often increased. Consequently, the most vital limitations of the dynamic latch comparator are the kickback noises generated by high transmission currents [ 15 ]. In addition, employing a transmission gate can also induce spikes at the differential input voltage signals, which affects the performance of the dynamic latch comparator due to random noise, input offset voltages, and component mismatch.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed and Low-Offset Dynamic Latch Comparator

Rahman

Reaz

Yin

et al. 2014

The Scientific World Journal

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Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.

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“…As the comparator is one of the block which limits the speed of the converter, its optimization is of utmost importance. The preamplifier stage amplifies the input signal to improve the comparator sensitivity and isolate the input of the comparator from switching noise coming from positive feedback stage [2]. The latch stage is used to determine which of the input signals is larger and extremely amplifies their difference.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

Yewale¹

2012

WET

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This paper presents an improved method for design of CMOS comparator based on a preamplifier-latch circuit driven by a clock. Design is intended to be implemented in Sigma-delta Analog-to-Digital Converter (ADC). The main advantage of this design is capable to reduce power dissipation and increase speed of an ADC. The design is simulated in 0.18 μm CMOS Technology with Cadence environment. Proposed design exhibits good accuracy and a low power consumption about 102 μW with operating sampling frequency 125 MHz and 1.8 V supply. Simulation results are reported and compared with earlier work done and improvements are observed in this work.

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A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters

Cited by 19 publications

References 5 publications

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

A High-Speed and Low-Offset Dynamic Latch Comparator

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

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A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters

Cited by 19 publications

References 5 publications

Analysis &amp; characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

Analysis &amp; characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

A High-Speed and Low-Offset Dynamic Latch Comparator

Design of Low Power and High Speed CMOS Comparator for A/D Converter Application

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Product

Resources

About

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology

Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology