A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS

Salimath, Arunkumar; Gonano, G.; Bonizzoni, Edoardo; Brambilla, D.; Botti, E.; Maloberti, Franco

doi:10.1109/iscas.2017.8050654

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…Many FHV-LSs have been proposed in the literature [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] to reduce the propagation delay. According to the structures, three topologies (Topology-I, Topology-II, and Topology-III) are summarized in Figure 1.…”

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

“…The CC-LS in [27] integrates two on-chip capacitors (both 60 fF) to shift the signal from V INL to V OH , but the rising/falling propagation delay of 1.45 ns/1.3 ns is large for the 180 nm process. The CC-LS in [28] achieves a 0.5 ns propagation delay with two 2 pF on-chip capacitors. The CC-LS in [29] achieves a 115 ps propagation delay by isolated low-voltage NMOS transistors and capacitive coupling, but the current mirror of the level shifter in [28,29] is not turned off after converting, resulting in high power consumption.…”

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

“…The CC-LS in [28] achieves a 0.5 ns propagation delay with two 2 pF on-chip capacitors. The CC-LS in [29] achieves a 115 ps propagation delay by isolated low-voltage NMOS transistors and capacitive coupling, but the current mirror of the level shifter in [28,29] is not turned off after converting, resulting in high power consumption.…”

Section: Review Of Conventional Fhv-lssmentioning

confidence: 99%

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A Novel Floating High-Voltage Level Shifter with Pre-Storage Technique

Yang

et al. 2022

Sensors

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This paper proposes a novel floating high-voltage level shifter (FHV-LS) with the pre-storage technique for high speed and low deviation in propagation delay. With this technology, the transmission paths from input to output are optimized, and thus the propagation delay of the proposed FHV-LS is reduced to as low as the sub-nanosecond scale. To further reduce the propagation delay, a pull-up network with regulated strength is introduced to reduce the fall time, which is a crucial part of the propagation delay. In addition, a pseudosymmetrical input pair is used to improve the symmetry of FHV-LS structurally to balance between the rising and falling propagation delays. Moreover, a start-up circuit is developed to initialize the output state of FHV-LS during the VDDH power up. The proposed FHV-LS is implemented using 0.3-µm HVCMOS technology. Post-layout simulation shows that the propagation delays and energy per transition of the proposed FHV-LS are 384 ps and 77.7 pJ @VH = 5 V, respectively. Finally, the 500-points Monte Carlo are performed to verify the performance and the stability.

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