A high speed low noise CMOS dynamic full adder cell

Meher, Preetisudha; Mahapatra, Kamalakanta

doi:10.1109/ccube.2013.6718575

Cited by 8 publications

(4 citation statements)

References 13 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The benchmarks we use to validate the proposed algorithm are dynamic three‐input NAND gate, three‐input AND gate and 1‐bit full adder [4, 5]. Circuits are implemented in 90 nm CMOS technology with a 1.2 V power supply.…”

Section: Final Design Performancementioning

confidence: 99%

“…Based on simulations, for some designs, the circuit with node-discharger may consume more power compared with conventional circuit, but the PDP still benefits from this technique. Final design performance: The benchmarks we use to validate the proposed algorithm are dynamic three-input NAND gate, three-input AND gate and 1-bit full adder [4,5]. Circuits are implemented in 90 nm CMOS technology with a 1.2 V power supply.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Low power‐delay‐product dynamic CMOS circuit design techniques

Xue

Ren

2017

Electron. lett.

View full text Add to dashboard Cite

Two low power-delay-product (PDP) dynamic CMOS circuit design techniques are proposed. The techniques can simply modify existing dynamic CMOS designs to improve dynamic circuit delay and PDP. Conventional benchmark circuits and the modified circuits using the proposed techniques are implemented in 90 nm CMOS technology with a 1.2 V power supply. Simulation results indicate that the proposed techniques can improve circuit PDP by 19.2 and 61.9% in two non-inverted dynamic benchmarks, respectively, and 6.2 and 33.72% in two inverted dynamic benchmarks, respectively.

show abstract

Section: Final Design Performancementioning

confidence: 99%

mentioning

confidence: 99%

Low power‐delay‐product dynamic CMOS circuit design techniques

Xue

Ren

2017

Electron. lett.

View full text Add to dashboard Cite

show abstract

“…The dynamic circuits have high speed, due to which it can be used in high-performance digital circuits. In recent years, many researchers [1][2][3][4] have reported that their work reduces the overall delay and power consumption. The speed of the dynamic circuits can be varied by having the proper load capacitance connected at the output, which will charge and discharge faster.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, more research work is being done on reducing the dynamic power in digital complementary metal oxide semiconductor (CMOS) circuits. The voltage keeper presented in [1,2] is used to keep the output at the desired value. When the clock is low, i.e.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of dynamic CMOS circuit based on node‐discharger and twist‐connected transistors

Vaithiyanathan¹,

Kumar²,

Rai³

et al. 2020

IET Computers & Digital Techniques

View full text Add to dashboard Cite

The incessant growth of devices such as mobile phones, digital cameras, and other portable electronic gadgets has led to a higher amount of research being dedicated to the low power digital and analogue circuits. In this study, a low powerdelay-product (PDP) dynamic complementary metal oxide semiconductor (CMOS) circuit design using small swing domino logic with twist-connected transistors is proposed. An improvement in PDP can be achieved by using a node-discharger circuit in the conventional design. The conventional benchmark and modified circuits are implemented in 90 nm CMOS technology with different power supplies, i.e. 1.2, 1, and 0.9 V. Furthermore, a decrease in voltage level for logic '1' and an increase in voltage level for logic '0' is achieved while maintaining the logic threshold accordingly at half of the supply voltage. So, the output voltage swing is reduced and the unnecessary nodes of the pull down network get discharged in pre-charge phase, eventually leading to an improvement when compared with conventional design in overall PDP by 43.21 and 46.83% for two inverted twoinput and three-input AND gate dynamic benchmarks, respectively, for a power supply of 1 V.

show abstract