Performance analysis of dynamic CMOS circuit based on node‐discharger and twist‐connected transistors

Abstract

The incessant growth of devices such as mobile phones, digital cameras, and other portable electronic gadgets has led to a higher amount of research being dedicated to the low power digital and analogue circuits. In this study, a low powerdelay-product (PDP) dynamic complementary metal oxide semiconductor (CMOS) circuit design using small swing domino logic with twist-connected transistors is proposed. An improvement in PDP can be achieved by using a node-discharger circuit in the conventional design. The conventional benchmark and modified circuits are implemented in 90 nm CMOS technology with different power supplies, i.e. 1.2, 1, and 0.9 V. Furthermore, a decrease in voltage level for logic '1' and an increase in voltage level for logic '0' is achieved while maintaining the logic threshold accordingly at half of the supply voltage. So, the output voltage swing is reduced and the unnecessary nodes of the pull down network get discharged in pre-charge phase, eventually leading to an improvement when compared with conventional design in overall PDP by 43.21 and 46.83% for two inverted twoinput and three-input AND gate dynamic benchmarks, respectively, for a power supply of 1 V.

Proposed time‐mode wide fan‐in NAND and NOR gates

“…Since both the precharging time and the average power consumption are dependent on the input pattern, half of the input bits is assumed to be at logic “1” and the other half is assumed to be at logic “0.” Although both the power consumption and the PDP of the scheme of Angeline and Bhaaskaran 47 are smaller than those of the proposed scheme, it must be noted that the load capacitance of this scheme is just the parasitic capacitance at the gate terminal of the keeper. Other schemes for comparison can be found in other studies 48–55 …”