A high-speed low-noise CMOS 16-channel charge-sensitive preamplifier ASIC for APD-based PET detectors

Abstract

Abstract--A high-speed, low-noise 16-channel amplifier IC has been fabricated in the HP 0.5 µ µ µ µm CMOS process. It is a prototype for use with a PET detector which uses a 4x4 avalanche photodiode (APD) array having 3 pF of capacitance and 75 nA of leakage current per pixel. The preamplifier must have a fast rise time (a few ns) in order to generate an accurate timing signal, low noise in order to accurately measure the energy of the incident gamma radiation, and high density in order to read out 2-D arrays of small (2 mm) pixels. A single channel consists of a charge-sensitive preamplifier followed by a pad-driving buffer. The preamplifier is reset by an NMOS transistor in the triode region which is controlled by an externally supplied current. The IC has 16 different gain settings which range from 2.085 mV/fC to 10.695 mV/fC. The gain is determined by four switched capacitors in the feedback loop. The switch state is set by two digital input lines which control a 64-bit shift register on the IC. A preamplifier 10-90% rise time as low as 2.7 ns with no external input load and 3.6 ns with a load of 5.8 pF was achieved. For the maximum gain setting and 5.8 pF of input load, the amplifier had 400 electrons of RMS noise at a peaking time of 0.7 µ µ µ µs. The IC i s powered by a +3.3 V supply drawing 60 mA.

Design of a Low-Noise Front-End Readout Circuit for CdZnTe Detectors

“…However, the bias current in the output leg should keep low in order to provide high impedance for high open-loop gain. Comparing the two cascode configurations shown in Figure 3, we can see that a split-leg straight cascode configuration is better than the folded cascode counterpart [8]. Because it maximizes the current in the input transistor by summing the current in both legs for highest g m while also providing high impedance at the output node.…”

A CAPACITIVE MEMs VERILOGA-BASED SENSOR SYSTEM FOR BUILDING INTEGRITY MONITORING

“…1, a single channel architecture readout is shown along with the fabricated ASIC. Commonly used read-out designs [Yi-Chen, 2008; Weng, 2005] use a modulation-demodulation architecture which demands high power levels. The proposed architecture of this work decouples the output of the sensor from the input of the charge amplifier (OTA) by a series capacitor C1 and two switches connected to arbitrary variable reference voltages VREF1 and VREF2.…”

“…In some of the modulation-demodulation architectures as reported [Suster, 2006;Yi-Chen, 2008;Weng, 2005;ADXL330, 2007], one particular design parameter such as linearity, resolution, bandwidth or gain is always matched to the sensor. This allows the optimization of power consumption at the expense of some performance.…”

“…Its gain can be set by the number of integration pulses N coming from the excitation voltage, optimizing then Signal-to-Noise Ratio (SNR) and bandwidth with power. In addition, the architecture suppresses motion artefacts [Yi-Chen, 2008;Weng, 2005], such as residual motion.…”

Development of 40 channel waveform sampling CMOS ASIC board for Positron Emission Tomography

“…The charge sensitive preamplifier [4] based on folded cascode topology is used to achieve the high-speed and the low-power dissipation. The first transistor's W/L ratio is set at a very large value for the large gain at the first step in order to obtain a high signal-to-noise ratio.…”