A high speed low power adder in dynamic logic base on transmission gate

Abstract

Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET transistor gain which in turn depends on transistor size. The power consumption in MOSFET is depends on the switching frequency, sub threshold leakage and switching time. In this paper, author proposed the speed and area efficient transistor base adder using static CMOS pass transistor logic, and shortened the longest critical path to decrease the total critical path delay. The design simulation on microwind layout tool calculates the worst-case delay in nanosecond and total power consumption in microwatt range.

Efficient Layout Design using Transmission Gate in 45nm Technology

“…The static and transient performance depends upon the availability of high-quality switches with low parasitic resistance and capacitance [10]- [11]. Its static power dissipation is constant and dynamic power is very less.…”

Design and Analysis of High Speed Low Power Hybrid Adder Using Transmission Gates

“…The inverter used in this circuit leads to dynamic power dissipation. It has low power consumption and high operating frequency and it also has a better cascading capability [10]. It uses hybrid logic style for its operation.…”

“…The power delay product and the area (less silicon area) are also better when compared to 10T and 14T adders. The noise margin is increased by the proper sizing of transistors in 3T XOR [10]. The threshold voltage loss is neglected.…”