A High-Speed MCML Logic Gate and Multiplexer Design in 45 nm CMOS Technology

Sivasakthi, M.; Radhika, P

doi:10.1109/icerect56837.2022.10059652

Cited by 6 publications

(2 citation statements)

References 20 publications

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“…CML is widely utilized because of its high resistance to common-mode signals. This characteristic also makes MCML a favored option in mixed-signal environments [2], [3]. High-performance analog and digital circuits may now be integrated on the same silicon substrate because of developments in semiconductor technology.…”

Section: Introductionmentioning

confidence: 99%

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Madheswaran,

Panneerselvam

2024

IJPEDS

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Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

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Section: Introductionmentioning

confidence: 99%

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Madheswaran,

Panneerselvam

2024

IJPEDS

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“…CML is widely used because of its inherent resistance to noise. This characteristic also Int J Elec & Comp Eng ISSN: 2088-8708  contributes to the popularity of MOS current mode logic (MCML) as a preferred choice among CML variants [3], [4]. The voltage-controlled oscillator commonly employs a complementary metal-oxide-semiconductor (CMOS) inverter as the delay unit.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

Madheswaran,

Panneerselvam

2024

IJECE

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This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

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A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

Sivasakthi,

Radhika

2023

Analog Integr Circ Sig Process

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A High-Speed MCML Logic Gate and Multiplexer Design in 45 nm CMOS Technology

Cited by 6 publications

References 20 publications

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

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