A high speed open source controller for FPGA Partial Reconfiguration

Abstract

Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

“…Previous experiments with traditional FPGAs showed that a custom solution can provide near theoretical peak reconfiguration throughput [2]. But such custom controllers were designed for non-processor systems, and hence did not provide a software-centric view or run-time reconfiguration management, making them difficult to port to the Zynq.…”

“…Currently supported methods of PR management on the Zynq fail to address this issue. Our previous work demonstrated that custom reconfiguration controllers can considerably reduce reconfiguration overhead in non-processor based systems [2]. In this paper, we present a new open-source reconfiguration controller and associated driver that significantly improve reconfiguration throughput in the Zynq while freeing the processor to work on other tasks.…”

Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs?

“…DPR significantly improved reconfiguration performance [13], however the efficiency of the traditional design approach for DPR is heavily impacted by how a design is partitioned and floorplanned [14], tasks that require FPGA expertise. Furthermore, the commonly used configuration mechanism is highly sub-optimal in terms of throughput [15]. Despite numerous efforts in reducing reconfiguration times and improving CAD tool support for dynamic reconfiguration of FPGA fabric [16], [13], the implementation of rapidly reconfigurable hardware accelerators is still difficult.…”

Microkernel dedicated for dynamic partial reconfiguration on ARM-FPGA platform

“…For example, in [8], a L4 kernel is ported to manage hardware and software tasks, but without using dynamic reconfiguration. In parallel, research in [9] discussed the reconfiguration management on Zynq platform at the application level, without using any operating system and thus with poor flexibility.…”