A high throughput configurable partially-parallel decoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

Abstract

In this paper, we are proposing a new architecture for the fast decoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective decoder architectures. In the present approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at the synthesis level. High levels of parallelism can be reached and hence high throughput achieved, thanks to the modular decoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through the implementation of different decoders related to DVB-T2 and DVB-S2 on FPGAs of the Altera Stratix II family. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.

High‐throughput 2 bit low‐density parity‐check forward error correction for C‐RAN optical fronthaul based on a hard‐decision algorithm

“…Considering a coding rate equal to 0.9, full-parallel hardware architecture [32] is too complex to be implemented for the fronthaul link in the C-RAN context. Since we are seeking for low-latency and highthroughput circuit, partially parallel architecture is recommended here [33][34][35][36]. In this section, we will put the emphasis on GDBF and BWGDBF implementation architectures.…”