International audienceLDPC codes are currently the most promising coding technique to achieve the Shannon capacity, making them very popular in modern telecommuncation applications. Despite the attractivity stemming from their effectiveness, encoding and decoding LDPC codes is a rather complex task, due to the size and structure of the codes, especially when considering the ever increasing need for higher throughput in communication networks. All these constraints are setting the demand for new encoding/decoding architectures very high. In this paper, we propose effective encoder and decoder architectures for the Quasi-Cycle subclass of LDPC codes. The main features being targeted are pre-synthesis configurability and high throughput. QC-LDPC codes exhibit a highly regular structure in their parity check matrices making easier the design process to obtain the high levels of architectural parallelism necessary to achieve the required high throughputs. In order to validate our design, several encoder and decoder were implemented on FPGAs of the Altera Stratix III and Xilinx Virtex4 using different code parameters (block length and code rate) for QC-LPDC codes from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.1 In) protocols. Throughputs up to 32 Gbits/s and 732 Mbits/s have been achieved for the encoder and decoder, respectively

In this paper, we are proposing a new architecture for the fast decoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective decoder architectures. In the present approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at the synthesis level. High levels of parallelism can be reached and hence high throughput achieved, thanks to the modular decoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through the implementation of different decoders related to DVB-T2 and DVB-S2 on FPGAs of the Altera Stratix II family. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.

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