A high throughput-rate architecture for 8*8 2D DCT

Sheu, Ming‐Hwa; Lee, J.-Y.; Wang, J.-F.; Suen, An-Nan; Liu, L.-Y.

doi:10.1109/iscas.1993.394041

Cited by 12 publications

(3 citation statements)

References 5 publications

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“…However, the input data elements of the kernel possess different signs so that it is not easy to apply the proposed memory-efficient approach directly to DCT realization. According to the symmetry property of DCT coefficients as shown in (5), we can write (7) as and the data elements in the matrix of (8) can be merged as (9) To separate the even and odd outputs in (9), we can obtain two smaller, perfect cyclic convolution forms as follows:…”

Section: A Algorithm Derivationmentioning

confidence: 99%

“…It has been widely adopted in many DSP applications such as discrete Fourier transform (DFT), DCT, convolution, and digital filters. Therefore, there has been great interest in reducing the ROM size required in Manuscript the implementation of the DA-based architectures [2], [7]- [9], [11]. Most of the DA-based designs exploit some memory reduction techniques such as the partial sum techniques and the offset binary coding (OBC) techniques [2], [8].…”

Section: Introductionmentioning

confidence: 99%

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A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

Chen

Guo²,

Chang³

et al. 2005

IEEE Trans. Circuits Syst. Video Technol.

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This paper presents a memory-efficient approach to realize the cyclic convolution and its application to the discrete cosine transform (DCT). We adopt the way of distributed arithmetic (DA) computation, exploit the symmetry property of DCT coefficients to merge the elements in the matrix of DCT kernel, separate the kernel to be two perfect cyclic forms, and partition the content of ROM into groups to facilitate an efficient realization of a one-dimensional (1-D) -point DCT kernel using ( -1)/2 adders or substractors, one small ROM module, a barrel shifter, and (( 1) 2) + 1 accumulators. The proposed memory-efficient design technique is characterized by rearranging the content of the ROM using the conventional DA approach into several groups such that all the elements in a group can be accessed simultaneously in accumulating all the DCT outputs for increasing the ROM utilization. Considering an example using 16-bit coefficients, the proposed design can save more than 57% of the delayarea product, as compare with the existing DA-based designs in the case of the 1-D seven-point DCT. Finally, a 1-D DCT chip was implemented to illustrate the efficiency associated with the proposed approach.

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Section: A Algorithm Derivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

Chen

Guo²,

Chang³

et al. 2005

IEEE Trans. Circuits Syst. Video Technol.

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show abstract

“…Advances in VLSI technology allow implementation of parallel processing on a single chip. Therefore, the approach proposed in Section 3 (new algorithm) can be exploited to design a fully systolic VLSI architecture avoiding the transposer that is required by classical architectures [39], [40]. The transposer requires a large area for global interconnection and time for loading and unloading.…”

Section: Vlsi Implementationmentioning

confidence: 99%

Parallel implementation of multidimensional transforms without interprocessor communication

Marino

Swartzlander

1999

IEEE Trans. Comput.

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ÐThis paper presents a modular algorithm which is suitable for computing a large class of multidimensional transforms in a general purpose parallel environment without interprocessor communication. Since it is based on matrix-vector multiplication, it does not impose restrictions on the size of the input data as many existing algorithms do. The method is fully general since it does not depend on the specific nature of the transform kernel and, therefore, it may be used for a wide variety of transforms. Moreover, since some one-dimensional Fast Fourier Transform algorithms map the input sequence onto two or more dimensions, the new method also may be employed to efficiently compute the 1D FFT in parallel. In addition, the proposed algorithm is exploited to derive a fully systolic VLSI architecture performing multidimensional transforms, which does not need the transposer required by classical architectures.

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2-D Discrete Cosine Transform (DCT) on Meshes with Hierarchical Control Modes

Kim

2005

Pattern Recognition and Image Analysis

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A high throughput-rate architecture for 8*8 2D DCT

Cited by 12 publications

References 5 publications

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

A memory-efficient realization of cyclic convolution and its application to discrete cosine transform

Parallel implementation of multidimensional transforms without interprocessor communication

2-D Discrete Cosine Transform (DCT) on Meshes with Hierarchical Control Modes

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