A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays

Na, Jun-Seok; Hong, Seong‐Kwan; Kwon, Oh‐Kyong

doi:10.1109/tcsii.2020.2972370

Cited by 13 publications

(5 citation statements)

References 15 publications

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“…Fig. 11 shows the schematic of the proposed D-V REF , which is a simplified 4-bit DAC-embedded amplifier [21], [22] without offset compensation to reduce the power. To interpolate between V H and V L according to the 4-bit digital code (n=3), there are sixteen different arrangements.…”

Section: Adaptive Voltage Referencementioning

confidence: 99%

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

Zeng

Chen

et al. 2023

IEEE Open J. Circuits Syst.

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This paper presents an electrocardiogram acquisition analog front-end (AFE) with a noise tolerant heartbeat (HB) detector. Source degradation and transconductance bootstrap techniques are incorporated into the AFE to reduce the 1/f noise of the amplifier. Furthermore, the chopper modulation, DC-servo loop (DSL) and pre-charge technology are combined to reduce interference from the environment. A mixed-signal implementation of HB detector with the symmetric-comparison loop is proposed to reduce the power consumption and area, which also suppresses motion artifact interference by adaptive thresholds. Implemented in 0.18 µm CMOS process, the circuit only occupies an area of 0.122 mm 2 and consumes 0.62 µW at a 1.2-V supply, of which AFE and HB detector consume 507 nW and 110 nW, respectively. Simulation results show that the gain and the CMRR of AFE range from 30-45 dB and 65-105 dB, respectively. The input-referred noise is 670 nVrms with a mid-band gain of 42 dB and a bandwidth ranging from 0.5 Hz to 1 kHz.

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Section: Adaptive Voltage Referencementioning

confidence: 99%

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

Zeng

Chen

et al. 2023

IEEE Open J. Circuits Syst.

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“…For example, if the data voltage range is 200 mV, achieving a 10‐bit grayscale requires dividing the range into 1024 levels, with each level having a voltage step of only 0.2 mV. Even the most accurate data driver reported to date exhibits an output voltage deviation of 5 mV between the channels 10–12 . Therefore, expanding the data voltage range is strongly required.…”

Section: Introductionmentioning

confidence: 99%

“…Even the most accurate data driver reported to date exhibits an output voltage deviation of 5 mV between the channels. [10][11][12] Therefore, expanding the data voltage range is strongly required.…”

Section: Introductionmentioning

confidence: 99%

4670‐PPI OLEDoS pixel circuit design for wide data voltage range in a 5 V 0.13 μm CMOS process

Shin,

Kim,

Choi

2024

J Soc Info Display

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OLEDoS displays hold great promise for AR/VR applications, but the ultra‐high pixel density required for microdisplays, exceeding several thousand PPI, presents significant challenges for pixel circuit design. Above all, the maximum OLED current of each OLEDoS sub‐pixel is extremely low, on the order of several nanoamperes or less, resulting in a data voltage range narrower than a few hundred millivolts. Consequently, for example, when expressing 10‐bit grayscale, designing data driver circuits to divide the data voltage range into 1024 levels becomes exceedingly challenging. Furthermore, circuit techniques that compensate for variations in transistor characteristics are nearly inapplicable due to the ultra‐small pixel area. This paper proposes a pixel circuit design method to expand the data voltage range for a 4670‐PPI OLEDoS display while considering current uniformity. The effectiveness of the proposed pixel circuit was verified through measurements on 40 × 120 pixel arrays fabricated in a 5 V 0.13 μm CMOS process.

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“…The source channel area is decreasing due to the previous works for area‐efficiency source driver, 8–12 but the probability of defects is increasing due to the higher density of source driver required for high resolution. This paper proposes an on‐the‐fly self‐repair (OFSR) circuit that can be used to repair image defects caused by vertical line defects on the display, similar to the built‐in self‐repair scheme in the memory cell 13–15 .…”

Section: Introductionmentioning

confidence: 99%

An OLED display driver IC with high‐gain fast‐slew circuit and on‐the‐fly self‐repair technique for high‐resolution display

Jo,

Yu,

Kim

et al. 2024

J Soc Info Display

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This paper presents an OLED display driver IC with high‐gain fast‐slew (HGFS) and on‐the‐fly self‐repair (OFSR) circuits for a spatial resolution of WQHD and a frame rate of 120 Hz. The proposed HGFS circuit increases the slewing current of the unity‐gain amplifier of the source driver when the input voltage is largely changed, reducing the settling time of the source driver as the resolution and frame rate increase. To enhance image quality by correcting line defects, the OFSR circuit replaces a faulty channel with a spare dummy channel. The OLED display driver IC was manufactured using a 28‐nm high‐voltage process with 8 V/20 V transistors and has 2880 source drivers for WQHD display. The measurement results indicate a horizontal line time of 2.7 μs with a slew rate of 7.675 V/μs, supporting WQHD resolution and 120‐Hz frame rate. The displayed image demonstrates that the vertical line defect has disappeared with the use of OFSR.

show abstract

A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays

Cited by 13 publications

References 15 publications

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector

4670‐PPI OLEDoS pixel circuit design for wide data voltage range in a 5 V 0.13 μm CMOS process

An OLED display driver IC with high‐gain fast‐slew circuit and on‐the‐fly self‐repair technique for high‐resolution display

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