A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

Abstract

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement

“…The dynamic range (DR) is 85.1 dB, and no significant noise is introduced compared with other ROIC or linearity-enhancing circuits. For a detailed comparison with other literature, see Table 1 .Table 1 shows the comparison between the linearity of the ROIC designed in this paper and references [1][2][3][4][5]. By comprehensive comparison of full well capacity, pixel size and DR, this design still achieves a good design index.…”

“…By comprehensive comparison of full well capacity, pixel size and DR, this design still achieves a good design index. It can be seen that the design method proposed in this paper not only guarantees linearity but also controls power consumption well and realize high DR. .Table 1 shows the comparison between the linearity of the ROIC designed in this paper and references [1][2][3][4][5]. By comprehensive comparison of full well capacity, pixel size and DR, this design still achieves a good design index.…”

The Effect of Pixel Design and Operation Conditions on Linear Output Range of 4T CMOS Image Sensors

“…Several notable studies have previously investigated the sources of nonlinearity in 4T pixels. Through improvements in circuit structure and methods such as digital calibration, these works have successfully mitigated the nonlinear response, achieving a final output linearity exceeding 99.95% [ 9 , 10 , 11 ]. Within the linear region, nonlinearity is mainly caused by the variation in electrical parameters with voltage, such as the small-signal voltage gain of the source follower (SF) and the capacitance of the FD (C FD ) node [ 12 ].…”

Electronics for Sensors

“…This Special Issue contains a selection of 16 papers covering photomultiplier tubes and silicon photomultipliers (PMTs and SiPMs) interfaces and applications [1][2][3], techniques for monitoring radiation levels [4,5], electronics for biomedical applications [6][7][8], design and applications of time-to-digital converters [9][10][11], interfaces for image sensors [12,13] and general-purpose theory and topologies for electronic interfaces [14][15][16].…”

“…The piezoelectric ultrasonic transducer was fabricated on top of the interface substrate. In [ 13 ], Li et al tackle some of the limitations that affect typical CMOS sensors such as linearity degradation caused by in-pixel circuitry and propose the introduction of a pre-distortion circuit based on a nonlinear ramp generator to replace linear ones commonly adopted.…”