IEEE Trans. VLSI Syst.
 2021
DOI: 10.1109/tvlsi.2021.3077084
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A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture

Mohsen Javadi
1
,
Hossein Miar Naimi
2
,
Saheed Tijani
3
et al.
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Cited by 3 publications
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References 31 publications
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New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB

Tao
1
,
Lei
2
,
Huang
3
et al. 2021
2021 IEEE 14th International Conference on ASIC (ASICON)
4
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New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB

Tao
1
,
Lei
2
,
Huang
3
et al. 2021
2021 IEEE 14th International Conference on ASIC (ASICON)
4
0
0
0
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Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures

Shams
1
,
Nabki
2
2022
IEEE Trans. VLSI Syst.
5
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Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications

Shams
1
,
Nabki
2
2023
IEEE Trans. VLSI Syst.
4
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